Oxide terminated trench MOSFET with three or four masks

• US 9,219,003 B2
• Filed: 01/27/2015
• Issued: 12/22/2015
• Est. Priority Date: 03/24/2010
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lui, Sik, Bhalla, Anup
• Primary Examiner(s): Harrison, Monica D
• Application Number:
  US14/606,900
• Publication Number:
  US 20150137225A1
• Time in Patent Office: 329 Days
• Field of Search: 438/270, 257/330, 257/331
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques encapsulating layers H01L21/56; After treatment of these layers; Selection of materials for these layers
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and body regions inside the active region are at source potential and source and body regions outside the isolation trench are at drain potential. The device can be made using a three-mask or four-mask process.

Claims

1. A method for making an insulator termination semiconductor device, comprising:

a) applying a trench mask to a semiconductor substrate;

b) etching the semiconductor substrate through the trench mask to form first and second sets of trenches, wherein the trenches in the second set are narrower than the trenches in the first set, wherein the first set includes an isolation trench that surrounds the second set of trenches;

c) forming a gate dielectric in the first and second sets of trenches;

d) doping a region of the semiconductor substrate under the isolation trench to form a channel stop;

e) depositing a conductive material into the first and second sets of trenches, wherein a thickness of the conductive material is selected to fill up the second set of trenches but not the isolation trench;

f) isotropically etching back the conductive material to form gate electrodes in the second set of trenches, wherein the conductive material is completely removed from the isolation trench;

g) filling the isolation trench with an insulator material to form an isolation structure that surrounds the gate electrodes;

h) forming a body layer in a top portion of the entire substrate;

i) forming a source layer in a top portion of the entire body layer;

wherein portions of the source layer and body layer inside a region surrounded by the isolation trench are at source potential and portions of the source layer and body layer that are outside the region surrounded by the isolation trench are at drain potential.

2. The method of claim 1 wherein forming the body layer and forming the source layer are performed without additional masks.

3. The method of claim 1, wherein the source and body layers inside a region surrounded by the isolation trench are at source potential and the source and body regions on the outside of the isolation trench are at drain potential.

4. The method of claim 1 wherein the active gates are formed in an active region and the isolation trench borders said active region.

5. The method of claim 1 wherein the semiconductor substrate further comprises a heavily doped bottom layer and a less heavily doped top layer, and wherein the isolation trench is formed such that the isolation trench penetrates into said heavily doped bottom layer.

6. The method of claim 1 wherein a) and b) are performed using only a single mask, and the first and second sets of trenches are etched simultaneously through openings in the single mask.

7. The method of claim 1 wherein a) and b) comprise:

applying a first trench mask to a semiconductor substrate;

etching the semiconductor substrate to form the first set of trenches;

applying a second trench mask to the semiconductor substrate; and

etching the semiconductor substrate to form the second set of trenches.

8. The method of claim 7 further comprising:

filling the first set of trenches with an insulator material; and

forming an additional trench in a top portion of the insulator material in at least one of the trenches in the second set other than the isolation trench.

9. The method of claim 8 wherein forming the additional trench is done using said second trench mask.

10. The method of claim 9 wherein c) comprises:

forming a gate dielectric in the second set of trenches; and

forming the conductive material in the second set of trenches and the additional trench to form gate electrodes in the second set of trenches and a gate runner in the additional trench.

11. An insulator termination semiconductor device comprising:

a plurality of gate trenches located in an active region, each of which includes a conductive gate electrode;

an isolation trench located in a termination region that surrounds the active region, wherein the isolation trench is filled with an insulator material to form an insulator termination for the semiconductor device;

a doped region of the semiconductor substrate under the isolation trench that forms a channel stop; and

source and body regions throughout the device, wherein portions of the source and body regions inside the active region are at source potential and portions of the source and body regions outside the insulation isolation trench are at drain potential.

12. The device of claim 11 wherein the semiconductor device further comprises a semiconductor substrate having a heavily doped bottom layer and a less heavily doped top layer, wherein the isolation trench penetrates into the heavily doped bottom layer.

13. The device of claim 11, wherein the isolation trench borders the active area.

14. The device of claim 11, further comprising a gate runner formed in the isolation trench.

15. A method for making a semiconductor device, comprising:

a) applying a trench mask to a semiconductor substrate;

b) etching the semiconductor substrate through the trench mask to form a gate runner trench;

c) forming a dielectric material in the gate runner trench;

d) forming a gate runner cavity in the dielectric material in the gate runner trench;

e) forming a set of gate trenches in an active device region, wherein the gate runner trench is wider than the gate trenches, wherein the gate runner trench intersects at least a portion of the gate trenches;

f) forming a gate dielectric in the gate trenches;

g) depositing a conductive material into the gate runner cavity and the gate trenches;

h) etching back the conductive material to form gate electrodes in the gate trenches and a gate runner in the gate runner cavity;

i) forming a body layer in a top portion of the entire substrate;

j) forming a source layer in a top portion of the entire body layer.

16. The method of claim 15, wherein forming the body layer and forming the source layer are performed without additional masks.

17. The method of claim 15, further comprising forming an insulator isolation trench around the active device region, wherein the source and body layers inside a region surrounded by an insulator isolation trench are at source potential and the source and body regions on the outside of the insulator isolation trench are at drain potential.

18. The method of claim 15, wherein d) and e) comprise:

applying a second trench mask to the semiconductor substrate after c); and

etching through openings in second trench mask to form the gate runner cavity and the gate trenches.

19. The method of claim 15, further comprising forming an insulator isolation trench around the active device region, wherein the gate runner trench intersects the insulator isolation trench, and wherein the gate runner in the gate runner cavity continues across the intersection between the gate runner trench and the insulator isolation trench.

20. A semiconductor device comprising:

a plurality of gate trenches located in an active region, each of which includes a conductive gate electrode;

a gate runner trench having a gate runner formed therein;

a doped region of the semiconductor substrate under the gate runner trench that forms a channel stop; and

source and body regions throughout the device, wherein portions of the source and body regions inside the active region are at source potential and portions of the source and body regions outside an insulator isolation trench are at drain potential.

21. The device of claim 20 further comprising a gate contact, wherein the gate contact and the gate runner trench are located in the active region between the gate trenches.

22. The device of claim 20 wherein the semiconductor device further comprises a semiconductor substrate having a heavily doped bottom layer and a less heavily doped top layer,

wherein the insulator isolation trench penetrates into the heavily doped bottom layer.