Die-to-die inductive communication devices and methods

• US 9,219,028 B1
• Filed: 12/17/2014
• Issued: 12/22/2015
• Est. Priority Date: 12/17/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Higgins, Leo M. III, Brauchler, Fred T.
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US14/573,674
• Time in Patent Office: 370 Days
• Field of Search: 257/777, 257/531
• US Class Current: 1/1
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29386 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/2939 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/8592 : Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/295 : containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/315 : the encapsulation having a cavity
• CPC Class Codes: H01L 23/49531 : the additional leads being a wiring board
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An embodiment of a packaged device includes first and second package leads, a first integrated circuit (IC) die, and a sub-assembly that includes a second IC die coupled to a substrate. The first IC die has a first coil, and the second IC die has a second coil. The first and second IC die are arranged within the device so that the first and second coils are aligned with each other across a gap between the first and second IC die, and the first and second IC die are galvanically isolated from each other. The first IC die is electrically coupled to the first package lead (e.g., with a wirebond), and a substrate bond pad is electrically coupled to the second package lead (e.g., with a wirebond). The sub-assembly also may include encapsulation at least over a wirebond that electrically couples the second IC die to the substrate.

Claims

1. A packaged device comprising:

a first package lead;

a second package lead;

a first integrated circuit (IC) die having a first coil proximate to a first die surface of the first IC die, wherein the first IC die is electrically coupled to the first package lead; and

a sub-assembly that includes

a first substrate having a first substrate surface, a second substrate surface, and a first substrate bond pad that is electrically coupled to the second package lead, and

a second IC die having a second coil proximate to a first die surface of the second IC die, wherein a second die surface of the second IC die is coupled to the first substrate surface, and

wherein the first IC die and the second IC die are arranged within the device so that the first die surface of the first IC die faces the first die surface of the second IC die, and the first coil and the second coil are aligned with each other across a gap between the first IC die and the second IC die, and wherein the first IC die and the second IC die are galvanically isolated from each other.

2. The device of claim 1, wherein:

the first substrate bond pad is exposed at the second substrate surface;

the first substrate has a second substrate bond pad exposed at the first substrate surface, wherein the second substrate bond pad is electrically connected to the first substrate bond pad through the first substrate;

the second IC die further includes a first IC bond pad exposed at the first die surface of the second IC die, wherein the first IC bond pad is electrically coupled to the second coil; and

the sub-assembly further comprises a first wirebond coupled between the second substrate bond pad and the first IC bond pad.

3. The device of claim 2, wherein the sub-assembly further comprises:

first encapsulant covering the first wirebond.

4. The device of claim 3, wherein:

the first encapsulant also covers the second IC die and the first substrate surface;

the first encapsulant has a substantially planar surface above the first die surface of the second IC die; and

the substantially planar surface of the first encapsulant is coupled to the first die surface of the first IC die.

5. The device of claim 4, further comprising:

adhesive material coupling the substantially planar surface of the first encapsulant to the first die surface of the first IC die.

6. The device of claim 3, wherein:

the first encapsulant has a glob top configuration over the first wirebond; and

the device further comprises adhesive material coupling the first die surface of the first IC die to the first die surface of the second IC die.

7. The device of claim 3, further comprising:

second encapsulant covering the sub-assembly, the first IC die, and portions of the first and second package leads.

8. The device of claim 1, further comprising:

one or more layers of dielectric material between the first and second coils.

9. The device of claim 1, further comprising:

a wirebond coupled between the first substrate bond pad and the second package lead.

10. The device of claim 1, wherein:

the first IC die further includes a first IC bond pad exposed at the first die surface of the first IC die; and

the device further comprises a wirebond coupled between the first IC bond pad and the first package lead.

11. The device of claim 1, further comprising:

inter-coil dielectric material between the first and second coils, wherein the inter-coil dielectric material has a thickness in a range of 25 micrometers to 400 micrometers, and a dielectric constant of the inter-coil dielectric material is in a range of 2.0 to 5.0.

12. The device of claim 1, further comprising:

a second substrate, wherein a second die surface of the first IC die is coupled to the second substrate, and wherein the second substrate, the first package lead, and the second package lead form portions of a lead frame.

13. The device of claim 1, wherein:

the first coil is formed from a plurality of first patterned conductors in a plurality of first metal layers that are separated by one or more first dielectric layers; and

the second coil is formed from a plurality of second patterned conductors in a plurality of second metal layers that are separated by one or more second dielectric layers.

14. The device of claim 1, wherein:

the first IC die further includes first communication circuitry coupled to the first coil; and

the second IC die further includes second communication circuitry coupled to the second coil.

15. The device of claim 1, wherein:

the first IC die further includes one or more additional first coils proximate to the first die surface of the first IC die; and

the second IC die further includes one or more additional second coils proximate to the first die surface of the second IC die, wherein each of the additional first coils is aligned with a corresponding one of the additional second coils across the gap.

16. A method of manufacturing an inductive communication device, the method comprising the steps of:

forming a sub-assembly by

coupling a first die surface of a first integrated circuit (IC) die to a first substrate surface of a first substrate, wherein the first IC die also has a second die surface and a first coil proximate to the second die surface, and wherein the first substrate also has a first substrate bond pad;

coupling the sub-assembly to a second IC die, wherein the second IC die has a second coil proximate to a first die surface of the second IC die, and wherein the sub-assembly is coupled to the second IC die so that the second die surface of the first IC die faces the first die surface of the second IC die, and the first coil and the second coil are aligned with each other across a gap between the first IC die and the second IC die, and wherein the first IC die and the second IC die are galvanically isolated from each other;

electrically coupling the second IC die to a first package lead; and

electrically coupling the first substrate bond pad to a second package lead.

17. The method of claim 16, wherein:

the first substrate bond pad is exposed at a second substrate surface of the first substrate; and

forming the sub-assembly further comprises coupling a wirebond between the first IC die and a second substrate bond pad that is exposed at the first substrate surface.

18. The method of claim 17, wherein forming the sub-assembly further comprises applying a first encapsulant to cover the wirebond.

19. The method of claim 18, wherein applying the first encapsulant further comprises also applying the first encapsulant to the first IC die and to the first substrate surface.

20. The method of claim 16, wherein coupling the sub-assembly to the second IC die comprises coupling the sub-assembly to the second IC die with an adhesive material.

21. The method of claim 16, wherein:

electrically coupling the second IC die to the first package lead comprises coupling a first wirebond between the second IC die and the first package lead; and

electrically coupling the first substrate bond pad to the second package lead comprises coupling a second wirebond between the first substrate bond pad and the second package lead.