3-D memory arrays
First Claim
1. A 3-D memory array, comprising:
- a plurality of elevationally extending strings of memory cells;
an array of select devices elevationally over and individually coupling with individual of the strings;
the select devices individually comprising a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric;
the individual channels being spaced from one another;
the gate material comprising a plurality of gate lines running along columns of the spaced channels elevationally over the strings;
dielectric material laterally between immediately adjacent of the gate lines, the dielectric material and the gate lines having longitudinally non-linear edges at an interface relative one another; and
the channels in immediately adjacent of the columns between the immediately adjacent gate lines being longitudinally staggered laterally across the dielectric material relative one another.
8 Assignments
0 Petitions
Accused Products
Abstract
A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.
88 Citations
26 Claims
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1. A 3-D memory array, comprising:
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a plurality of elevationally extending strings of memory cells; an array of select devices elevationally over and individually coupling with individual of the strings;
the select devices individually comprising a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric;
the individual channels being spaced from one another;
the gate material comprising a plurality of gate lines running along columns of the spaced channels elevationally over the strings;dielectric material laterally between immediately adjacent of the gate lines, the dielectric material and the gate lines having longitudinally non-linear edges at an interface relative one another; and the channels in immediately adjacent of the columns between the immediately adjacent gate lines being longitudinally staggered laterally across the dielectric material relative one another. - View Dependent Claims (2, 3, 4)
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5. A 3-D memory array, comprising:
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a plurality of elevationally extending strings of memory cells; an array of select devices elevationally over and individually coupling with individual of the strings;
the select devices individually comprising a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric;
the individual channels being spaced from one another;
the gate material comprising a plurality of gate lines running along columns of the spaced channels elevationally over the strings;dielectric material laterally between immediately adjacent of the gate lines, the dielectric material and the gate lines having longitudinally non-linear edges at an interface relative one another; and multiple columns of spaced channels in individual of the gate lines. - View Dependent Claims (6, 7)
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8. A 3-D memory array, comprising:
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a plurality of elevationally extending strings of memory cells; an array of select devices elevationally over and individually coupling with individual of the strings;
the select devices individually comprising a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric;
the individual channels being spaced from one another;
the gate material comprising a plurality of gate lines running along columns of the spaced channels elevationally over the strings;dielectric material laterally between immediately adjacent of the gate lines, the dielectric material and the gate lines having longitudinally non-linear edges at an interface relative one another; and the memory cells being serially coupled within the individual strings, the strings individually comprising an active area pillar extending through elevationally inner tiers, the inner tiers individually comprising charge storage structures adjacent the pillars and access lines adjacent the charge storage structures, the select devices comprising select gate drains (SGD'"'"'s).
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9. A 3-D memory array, comprising:
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a plurality of elevationally extending strings of memory cells; an array of select devices elevationally over and individually coupling with individual of the strings;
the select devices individually comprising a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric;
the individual channels being spaced from one another;
the gate material comprising a plurality of gate lines running along columns of the spaced channels elevationally over the strings;dielectric material laterally between immediately adjacent of the gate lines, the dielectric material and the gate lines having longitudinally non-linear edges at an interface relative one another; the channels in the columns with respect to immediately adjacent of the gate lines being longitudinally equidistantly staggered relative one another; and the select devices across the dielectric material having pitch P2 equal to
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10. A 3-D memory array, comprising:
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a plurality of elevationally extending strings of memory cells; an array of select devices elevationally over and individually coupling with individual of the strings, the select devices comprising adjacent longitudinally curvilinear gate lines laterally separated by dielectric material; and the memory cells being serially coupled within the individual strings, the strings individually comprising an active area pillar extending through elevationally inner tiers, the inner tiers individually comprising charge storage structures adjacent the pillars and access lines adjacent the charge storage structures. - View Dependent Claims (11, 12)
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13. A 3-D memory array, comprising:
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a plurality of elevationally extending strings of memory cells; an array of select devices elevationally over and individually coupling with individual of the strings, the select devices comprising gate lines laterally separated by dielectric material; the select devices across the dielectric material have pitch equal to select device channel width plus twice gate dielectric width plus gate line material width between the gate dielectric and the dielectric material plus dielectric material width; and individual of the gate lines comprising multiple columns of spaced select device channels individually surrounded by material of the individual gate line; and pitch of the select devices across immediately adjacent of the gate lines being less than pitch of the select devices within individual of the gate lines. - View Dependent Claims (14)
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15. A 3-D memory array, comprising:
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a plurality of elevationally extending strings of memory cells; an array of select devices elevationally over and individually coupling with individual of the strings, the select devices comprising gate lines laterally separated by dielectric material; the select devices across the dielectric material have pitch equal to select device channel width plus twice gate dielectric width plus gate line material width between the gate dielectric and the dielectric material plus dielectric material width; and the memory cells being serially coupled within the individual strings, the strings individually comprising an active area pillar extending through elevationally inner tiers, the inner tiers individually comprising charge storage structures adjacent the pillars and access lines adjacent the charge storage structures, the select devices comprising select gate drains (SGD'"'"'s).
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16. A 3-D memory array, comprising:
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a plurality of elevationally extending strings of memory cells; an array of select devices elevationally over and individually coupling with individual of the strings, the select devices comprising gate lines laterally separated by dielectric material, the select devices comprising a column of spaced channels within individual of the gate lines, the channels in the columns with respect to immediately adjacent of the gate lines being longitudinally equidistantly staggered relative one another; the select devices across the dielectric material have pitch P2 equal to
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17. A 3-D memory array, comprising:
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a plurality of elevationally extending strings of memory cells; an array of select devices elevationally over and individually coupling with individual of the strings, the select devices comprising gate lines laterally separated by dielectric material, the select devices comprising a column of spaced channels within individual of the gate lines, the channels in the columns with respect to immediately adjacent of the gate lines being longitudinally equidistantly staggered relative one another; the select devices across the dielectric material have pitch P2 equal to
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18. A 3-D memory array, comprising:
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a plurality of elevationally extending strings of memory cells; an array of select devices elevationally over and individually coupling with individual of the strings, the select devices comprising gate lines laterally separated by dielectric material, individual of the gate lines comprising multiple columns of spaced select device channels individually surrounded by material of the individual gate line; and pitch of the select devices across immediately adjacent of the gate lines being less than pitch of the select devices within individual of the gate lines. - View Dependent Claims (19)
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20. A 3-D memory array, comprising:
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a plurality of serially-coupled and elevationally extending strings of memory cells, the strings individually comprising an active area pillar extending through elevationally inner tiers, the inner tiers individually comprising charge storage structures adjacent the pillars and access lines adjacent the charge storage structures; an elevationally outer tier comprising an array of select gate drains (SGD'"'"'s) that individually couple with the individual strings;
the SGD'"'"'s individually comprising a channel pillar elevationally over and coupled with one of the active area pillars, gate dielectric surrounding the channel pillar, and gate material surrounding the gate dielectric;
the gate material comprising a plurality of SGD gate lines in the outer tier running along columns of the channel pillars;
the channel pillars in immediately adjacent of the columns between the immediately adjacent gate lines being longitudinally equidistantly staggered relative one another; anddielectric material in the outer tier laterally separating immediately adjacent of the gate lines, the dielectric material and the gate lines having longitudinally curvilinear edges at an interface relative one another. - View Dependent Claims (21, 22, 23, 24, 25, 26)
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Specification