Metal gate semiconductor device

• US 9,219,124 B2
• Filed: 06/27/2014
• Issued: 12/22/2015
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry-Hak Lay, Zhu, Ming, Lin, Hui Wen, Young, Bao Ru
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US14/318,226
• Publication Number:
  US 20140374835A1
• Time in Patent Office: 543 Days
• Field of Search: 257/407, 257/775
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor device including a first gate structure associated with a first type of transistor and a second gate structure of a second type of transistor. The first gate structure includes a capping layer, a first metal layer having a first type of work function on the capping layer, and a second metal layer having a second type of work function, overlying the first metal layer and a fill layer on the second metal layer. The second type of work function is different than the first type of work function. The second gate structure includes the gate dielectric and the second metal layer formed on the gate dielectric, and the fill layer on the second metal layer.

Claims

1. A device, comprising:

a first gate structure of an NMOS device, the first gate structure including;

a first type of work function material;

a second type of work function material overlying the first type of work function material, wherein the second type of work function material includes oxygen; and

a fill layer overlying the second type of work function material; and

a second gate structure of a PMOS device, the second gate structure including;

the second type of work function material; and

the fill layer overlying the second type of work function material.

2. The device of claim 1, wherein the fill layer includes a blocking layer and a filler metal layer.

3. The device of claim 1, wherein each of the first and second gate structures include a gate dielectric layer underlying the first or second type of work function material, and wherein the gate dielectric layer includes a high-k dielectric material.

4. The device of claim 1, wherein the second type of work function material is TiON.

5. The device of claim 1, wherein the first type of work function material includes a bi-layer including a capping layer and a metal layer.

6. A semiconductor device, comprising:

a first gate structure associated with a NMOS transistor, wherein the first gate structure includes a gate dielectric, a capping layer, a first metal layer on the capping layer, and a second metal layer overlying the first metal layer, wherein the first metal layer is an n-type metal; and

a second gate structure associated with a PMOS transistor, wherein the second gate structure includes the gate dielectric and the second metal layer formed directly on the gate dielectric.

7. The device of claim 6, wherein the second gate structure does not include the first metal layer.

8. The device of claim 6, wherein the second metal layer is a p-type metal.

9. The device of claim 6, wherein the capping layer is not disposed in the second gate structure.

10. The device of claim 6, wherein the capping layer is lanthanum oxide.

11. The device of claim 6, wherein the first gate structure further comprises:

a fill layer disposed on the second metal layer, wherein the fill layer includes;

a blocking layer and a filler layer.

12. The device of claim 11, wherein the second gate structure further comprises:

the fill layer comprising the blocking layer and the filler layer on the second metal layer.

13. The device of claim 12, wherein the blocking layer is a metal nitride and the filler layer is a metal layer.

14. A semiconductor device comprising:

a first gate structure associated with a first type of transistor, wherein the first gate structure includes a capping layer, a first metal layer having a first type of work function on the capping layer, and a second metal layer having a second type of work function, overlying the first metal layer, wherein the second type of work function is different than the first type of work function, and a fill layer on the second metal layer;

a second gate structure associated with a second type of transistor, wherein the portion of the second gate structure includes the gate dielectric and the second metal layer formed on the gate dielectric, and the fill layer on the second metal layer, wherein the second gate structure does not include the first metal layer; and

an isolation region in a semiconductor substrate, the isolation region interposing the first and second gate structures.

15. The device of claim 14, wherein the second metal layer includes TiON.

16. The device of claim 14, further comprising:

a lanthanum oxide layer disposed under the second metal layer.

17. The device of claim 14, wherein the first type of transistor is an n-type of transistor.