Semiconductor device and fabricating method thereof

• US 9,219,148 B2
• Filed: 06/18/2013
• Issued: 12/22/2015
• Est. Priority Date: 08/23/2012
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Shin, Hyun Kwang
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): MAZUMDER, DIDARUL A
• Application Number:
  US13/920,634
• Publication Number:
  US 20140054690A1
• Time in Patent Office: 917 Days
• Field of Search: 257329-333, 257341-342
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device and a fabricating method thereof are provided, in which the semiconductor device includes a semiconductor substrate with a trench formed therein, a bottom electrode placed at a lower inner portion of the trench, the bottom electrode having an uneven upper surface, an insulating layer formed on an upper portion of the bottom electrode and on a sidewall of the trench, and a top electrode placed at an upper portion of the bottom electrode inside the trench, the top electrode having a top electrode which is uneven, in which the top electrode is so configured that the top electrode is inclined toward a center portion.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate comprising a trench formed therein;

a bottom electrode formed inside the trench;

a top electrode formed inside the trench and above the bottom electrode; and

an insulating layer separating the top electrode from the bottom electrode,

wherein the insulating layer has an uneven upper surface, and an additional depression having a shape of a key hole with a substantially vertical sidewall is formed in the uneven upper surface;

the top electrode has an uneven lower surface; and

the uneven lower surface of the top electrode comprises a curved surface with a protrusion in a center portion of the trench that protrudes toward the bottom electrode to fill the additional depression having the shape of the key hole.

2. The semiconductor device of claim 1, wherein the uneven lower surface of the top electrode is inclined toward the center portion of the trench;

an upper surface of the bottom electrode is inclined toward the center portion of the trench; and

an upper surface of the top electrode is inclined toward the center portion of the trench.

3. The semiconductor device of claim 1, wherein the curved surface of the top electrode protrudes toward an upper uneven surface of the bottom electrode.

4. The semiconductor device of claim 1, wherein an upper surface of the bottom electrode has a center area that is depressed toward a bottom surface of the trench.

5. The semiconductor device of claim 1, wherein the bottom electrode comprises an undoped poly silicon, and the top electrode comprises a doped poly silicon.

6. The semiconductor device of claim 1, further comprising:

a sacrificial layer formed on a bottom surface and a lower sidewall of the trench;

a burial layer formed above the top electrode in the trench; and

a metal barrier layer formed above the burial layer.

7. The semiconductor device of claim 6, wherein the burial layer comprises at least one of a high temperature low pressure deposition (LPCVD) oxide layer, a borophosphosilicate glass (BPSG), a phosphosilicate glass (PSG) or a tetraethoxy silane (TEOS) film.

8. The semiconductor device of claim 6, wherein the metal barrier layer comprises at least one of titanium (Ti) or titanium nitrate (TiN).

9. The semiconductor device of claim 6, wherein the metal barrier layer has a multilayer structure.

10. The semiconductor device of claim 6, further comprising a metal electrode formed on the metal barrier layer, the metal electrode comprising aluminum (Al).

14. The semiconductor device of claim 1, wherein the insulating layer comprises:

a poly oxide layer formed on an upper surface of the bottom electrode; and

a gate oxide layer formed on a sidewall of the trench.

15. The semiconductor device of claim 14, wherein the poly oxide layer comprises an uneven surface formed on the upper surface of the bottom electrode.

16. The semiconductor device of claim 14, wherein the poly oxide layer is formed during an oxidization of an upper surface of the bottom electrode, and the gate oxide layer is formed during an oxidization of the semiconductor substrate.

17. The semiconductor device of claim 14, further comprising a sidewall oxide layer formed on a sidewall of the bottom electrode within the trench.

18. The semiconductor device of claim 17, wherein the poly oxide layer has a thickness equal to, or greater than, that of the gate oxide layer, and the sidewall oxide layer has a greater thickness than the poly oxide layer and the gate oxide layer.

19. The semiconductor device of claim 17, further comprising:

a sacrificial layer formed on a bottom surface and a lower sidewall of the trench; and

a sacrificial bottom oxide layer that is formed on a lower surface of the bottom electrode, the sidewall oxide layer having a greater thickness than the sacrificial bottom oxide layer.

11. A semiconductor device, comprising:

a semiconductor substrate comprising a trench formed therein;

a bottom electrode formed inside the trench;

a top electrode formed inside the trench and above the bottom electrode;

an insulating layer separating the top electrode from the bottom electrode and extending laterally to cover the semiconductor substrate;

a burial layer formed above the top electrode in the trench; and

a metal barrier layer formed above the burial layer and extending laterally to contact the semiconductor substrate via a contact hole formed in the insulating layer,

wherein the insulating layer has an uneven upper surface, and an additional depression having a shape of a key hole with a substantially vertical sidewall is formed in the uneven upper surface; and

the top electrode has an uneven lower surface with a protrusion in a center portion of the trench that protrudes toward the bottom electrode to fill the additional depression having the shape of the key hole.

12. The semiconductor device of claim 11, wherein the semiconductor substrate comprises, at a site where the contact hole is formed:

a P-type body contact region contacting the metal barrier layer;

one or more N-type source regions contacting the metal barrier layer and formed adjacent to the P-type body contact region, and having a doping characteristic different from that of the P-type body contact region;

a body layer formed at a lower portion of the P-type body contact region and the N-type source region; and

an epilayer formed at a lower portion of the body layer.

13. The semiconductor device of claim 12, further comprising:

a metal electrode formed above the top electrode; and

a drain region formed in the semiconductor substrate to form a channel between the drain region and the N-type source region.

20. A method of fabricating a semiconductor device, comprising:

forming a trench in a semiconductor substrate; and

forming a bottom electrode inside the trench;

forming an insulating layer on the bottom electrode, the insulating layer having an uneven surface, and an additional depression having a shape of a key hole with a substantially vertical sidewall formed in the uneven upper surface;

and forming a top electrode such that the insulating layer is disposed between the top electrode and the bottom electrode inside the trench,

wherein a lower surface of the top electrode comprises a curved surface with a protrusion in a center portion of the trench that protrudes toward the bottom electrode to fill the additional depression having the shape of the key hole.

21. The method of claim 20, wherein an upper surface of the top electrode is curved shape.

22. The method of claim 20, further comprising:

forming a sacrificial layer on a bottom surface and a lower side wall of the trench before forming the bottom electrode in the trench,

forming a burial layer above the top electrode in the trench; and

forming a metal barrier layer above the burial layer,

wherein the forming of the burial layer comprises forming at least one of;

a high temperature low pressure deposition (LPCVD) oxide layer, a borophosphosilicate glass (BPSG), a phosphosilicate glass (PSG) or a tetraethoxy silane (TEOS) film.

23. The method of claim 22, wherein the forming of the metal barrier layer comprises forming a contact hole through a portion of the insulating layer covering the semiconductor substrate to form the metal barrier layer in contact with an exposed surface of the semiconductor substrate.

24. The method of claim 20, wherein the forming of the insulating layer on the bottom electrode comprises thermally oxidizing a polysilicon that forms the bottom electrode to form a poly oxide layer, and the key hole is formed within the poly oxide layer through an etch-back process of the polysilicon.