Semiconductor device with vertical transistor channels and a compensation structure

• US 9,219,149 B2
• Filed: 07/05/2013
• Issued: 12/22/2015
• Est. Priority Date: 07/05/2013
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies Dresden GmbH (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Dresden GmbH (Infineon Technologies AG)
• Inventors: Mauder, Anton, Kowalik-Seidl, Katarzyna, Weis, Rolf, Wahl, Uwe
• Primary Examiner(s): GORDON, MATTHEW E
• Application Number:
  US13/935,628
• Publication Number:
  US 20150008517A1
• Time in Patent Office: 900 Days
• Field of Search: 257/334, 257/E29.257, 438/270
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

A semiconductor device includes transistor cells with vertical channels perpendicular to a first surface of a semiconductor portion. A buried compensation structure in the semiconductor portion between the transistor cells and a second surface of the semiconductor portion parallel to the first surface includes first areas and second areas. The first and second areas are alternatingly arranged along a lateral direction parallel to the first surface. A contiguous impurity layer of a first conductivity type separates the transistor cells from the buried compensation structure.

Claims

1. A semiconductor device, comprising:

transistor cells arranged at a first pitch and having double-gated and fully depletable vertical channels perpendicular to a first surface of a semiconductor portion;

a buried compensation structure between the transistor cells and a second surface of the semiconductor portion parallel to the first surface, the compensation structure comprising first areas and second areas alternatingly arranged along a lateral direction parallel to the first surface wherein the first areas are arranged at a second pitch that differs from the first pitch, wherein at least one of;

a material composition, and a conductivity type, of the first area, is different from the second area; and

a contiguous impurity layer of a first conductivity type separating the transistor cells and the compensation structure.

2. The semiconductor device according to claim 1, wherein

the first areas have the first conductivity type and the second areas have a complementary, second conductivity type and the first and second areas form pn junctions.

3. The semiconductor device according to claim 2, wherein

a laterally integrated impurity concentration in the first areas deviates by not more than 10% from a laterally integrated impurity concentration in the second areas at the same distance to the first surface.

4. The semiconductor device according to claim 1, wherein

the second areas are electrically connected with each other and a conductive structure.

5. The semiconductor device according to claim 1, wherein

the contiguous impurity layer is structurally connected with the first areas.

6. The semiconductor device according to claim 1, further comprising:

gate electrodes between the first surface and the contiguous impurity layer; and

active transistor areas in semiconductor mesas between the gate electrodes.

7. The semiconductor device according to claim 6, wherein

the second areas are electrically connected with a first electrode structure electrically connected to source zones in the active transistor areas.

8. The semiconductor device according to claim 6, wherein

the gate electrodes are dielectrically insulated from source zones in the active transistor areas.

9. The semiconductor device according to claim 8, wherein

the active transistor areas comprise channel zones of a conductivity type of the first areas, the channel zones structurally connecting the source zones and the contiguous impurity layer, and

a mean net impurity concentration in the source zones exceeds at least five times a mean net impurity concentration in the channel zones.

10. The semiconductor device according to claim 9, wherein

the transistor cells are configured as depletion type field effect transistor cells and gate dielectrics dielectrically insulate the gate electrodes from the channel zones.

11. The semiconductor device according to claim 9, wherein

the transistor cells are configured as junction field effect transistor cells and the gate electrodes directly adjoin the channel zones.

12. The semiconductor device according to claim 8, wherein

the active transistor areas include body zones of a conductivity type opposite to a conductivity type of the first areas, the body zones structurally separating the source zones from a drift layer including the contiguous impurity layer.

13. The semiconductor device according to claim 12, wherein

the transistor cells are configured as enhancement type field effect transistor cells and gate dielectrics dielectrically insulate the gate electrodes from the body zones.

14. The semiconductor device according to claim 1, wherein

the transistor cells are stripe-shaped and longitudinal axes of the transistor cells extend in a first lateral direction parallel to the first surface, and

the second areas are stripe-shaped and longitudinal axes of the second areas extend in a second lateral direction intersecting the first lateral direction.

15. The semiconductor device according to claim 1, further comprising:

dielectric layers which dielectrically insulate the second areas from the first areas.

16. The semiconductor device according to claim 1, wherein

each second area includes at least a first section and a second section, the first and second sections arranged in a vertical direction perpendicular to the first surface.

17. The semiconductor device according to claim 16, wherein

a thickness of a first dielectric layer dielectrically insulating the first sections differs from a thickness of a second dielectric layer dielectrically insulating the second sections.

18. The semiconductor device according to claim 1, further comprising:

a drain layer electrically connected to the first areas and a second electrode structure, the second electrode structure directly adjoining the second surface.