Semiconductor device and manufacturing method thereof

• US 9,219,162 B2
• Filed: 05/27/2014
• Issued: 12/22/2015
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun
• Primary Examiner(s): Nhu, David
• Application Number:
  US14/287,320
• Publication Number:
  US 20140264327A1
• Time in Patent Office: 574 Days
• Field of Search: 257/607, 257/43, 257/213, 257/288, 257/914, 257/316, 257/314, 257/415, 257/E21.051, 257/E21.17, 257/E21.37, 257/E21.218, 257/E21.227, 257/E21.229, 257/E21.249, 257/E21.311
• US Class Current: 1/1
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer over an insulating surface;

a first conductive layer and a second conductive layer over the oxide semiconductor layer;

a gate insulating layer over the first conductive layer and the second conductive layer; and

a gate electrode over the gate insulating layer,

wherein the gate electrode overlaps with a portion of the first conductive layer and a portion of the second conductive layer with the gate insulating layer therebetween, and

wherein the oxide semiconductor layer comprises a nanocrystal with a size greater than or equal to 1 nm and smaller than or equal to 20 nm.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium and zinc.

3. The semiconductor device according to claim 1, wherein a hydrogen concentration of the oxide semiconductor layer is smaller than or equal to 5×

10¹⁹/cm³.

4. The semiconductor device according to claim 1, wherein a carrier concentration of the oxide semiconductor layer is smaller than or equal to 1×

10¹² /cm³.

5. A semiconductor device comprising:

an oxide semiconductor layer over an insulating surface;

a first conductive layer and a second conductive layer over the oxide semiconductor layer;

a gate insulating layer over the first conductive layer and the second conductive layer; and

a gate electrode over the gate insulating layer,

wherein the gate electrode overlaps with a portion of the first conductive layer and a portion of the second conductive layer with the gate insulating layer therebetween, and

wherein the oxide semiconductor layer comprises a nanocrystal with a size greater than or equal to 1 nm and smaller than or equal to 20 nm,

wherein a ratio of the nanocrystal in the oxide semiconductor layer is larger than or equal to 90%.

6. The semiconductor device according to claim 5, wherein the oxide semiconductor layer comprises indium, gallium and zinc.

7. The semiconductor device according to claim 5, wherein a hydrogen concentration of the oxide semiconductor layer is smaller than or equal to 5×

10¹⁹/cm³.

8. The semiconductor device according to claim 5, wherein a carrier concentration of the oxide semiconductor layer is smaller than or equal to 1×

10¹² cm³.

9. A semiconductor device comprising:

an oxide semiconductor layer over an insulating surface;

a first conductive layer and a second conductive layer over the oxide semiconductor layer;

a third conductive layer over the first conductive layer;

a fourth conductive layer over the second conductive layer;

a gate insulating layer over the third conductive layer and the fourth conductive layer; and

a gate electrode over the gate insulating layer,

wherein the gate electrode overlaps with a portion of the third conductive layer and a portion of the fourth conductive layer with the gate insulating layer therebetween, and

wherein the oxide semiconductor layer comprises a nanocrystal with a size greater than or equal to 1 nm and smaller than or equal to 20 nm.

10. The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises indium, gallium and zinc.

11. The semiconductor device according to claim 9, wherein a hydrogen concentration of the oxide semiconductor layer is smaller than or equal to 5×

10¹⁹ /cm³.

12. The semiconductor device according to claim 9, wherein a carrier concentration of the oxide semiconductor layer is smaller than or equal to 1×

10¹² /cm³.

13. A semiconductor device comprising:

an oxide semiconductor layer over an insulating surface;

a first conductive layer and a second conductive layer over the oxide semiconductor layer;

a third conductive layer over the first conductive layer;

a fourth conductive layer over the second conductive layer;

a gate insulating layer over the third conductive layer and the fourth conductive layer; and

a gate electrode over the gate insulating layer,

wherein the gate electrode overlaps with a portion of the third conductive layer and a portion of the fourth conductive layer with the gate insulating layer therebetween, and

wherein the oxide semiconductor layer comprises a nanocrystal with a size greater than or equal to 1 nm and smaller than or equal to 20 nm,

wherein a ratio of the nanocrystal in the oxide semiconductor layer is larger than or equal to 90%.

14. The semiconductor device according to claim 13, wherein the oxide semiconductor layer comprises indium, gallium and zinc.

15. The semiconductor device according to claim 13, wherein a hydrogen concentration of the oxide semiconductor layer is smaller than or equal to 5×

10¹⁹ /cm³.

16. The semiconductor device according to claim 13, wherein a carrier concentration of the oxide semiconductor layer is smaller than or equal to 1×

10¹² /cm³.