Multi-bit ferroelectric memory device and methods of forming the same

• US 9,219,225 B2
• Filed: 10/31/2013
• Issued: 12/22/2015
• Est. Priority Date: 10/31/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gealy, F Daniel, Ramaswamy, D. V. Nirmal, Mouli, Chandra V, Karda, Kamal M
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US14/068,887
• Publication Number:
  US 20150117084A1
• Time in Patent Office: 782 Days
• Field of Search: 365/145, 257/421, 438/3
• US Class Current: 1/1
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.

Claims

1. A method for forming a memory device, comprising:

forming a first ferroelectric material on a first side of a via;

removing a material to expose a second side of the via; and

forming a second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.

2. The method of claim 1, wherein the first ferroelectric material and the second ferroelectric material have different thicknesses.

3. The method of claim 1, further comprising changing a polarization of the first ferroelectric material utilizing a first bias and changing the second ferroelectric material utilizing a second bias.

4. The method of claim 3, wherein the polarization of the second ferroelectric material is not changed when changing the polarization of the first ferroelectric material utilizing the first bias.

5. The method of claim 3, wherein the polarization of the first ferroelectric material is changed when changing the second ferroelectric material utilizing a second bias.

6. The method of claim 1, further comprising assigning a state to a number of polarization combinations between a polarization of the first ferroelectric material and a polarization of the second ferroelectric material.

7. A method for forming a number of ferroelectric memory devices, comprising:

forming a via;

forming a first ferroelectric material on an interior side of the via;

forming a poly material on the first ferroelectric material on the interior side of the via;

exposing an exterior side of the via;

forming a second ferroelectric material on the exterior side of the via; and

removing the poly material to form a number of ferroelectric memory devices.

8. The method of claim 7, wherein forming the first ferroelectric material on the interior side of the via includes forming the first ferroelectric material on the interior side of the via prior to forming the poly material on the first ferroelectric material.

9. The method of claim 8, wherein forming the poly material includes protecting the first ferroelectric material on the interior side of the via while exposing the exterior side of the via.

10. The method of claim 7, wherein forming the first ferroelectric material on the interior side of the via comprises forming the first ferroelectric material at different thickness than the second ferroelectric material formed on the exterior side of the via.

11. The method of claim 7, wherein forming the first ferroelectric material on the interior side of the via includes forming the first ferroelectric material with a different coercive field than the second ferroelectric material formed on the exterior side of the via.

12. A memory device, comprising:

a first ferroelectric material formed on an interior sidewall of a via and having a first thickness; and

a second ferroelectric material formed on an exterior sidewall of the via and having a second thickness.

13. The memory device of claim 12, wherein the first ferroelectric material at the first thickness has a first coercive field and the second ferroelectric material at the second thickness has a second coercive field.

14. The memory device of claim 12, wherein a first bias changes a polarization of the first ferroelectric material on the first side without changing a polarization of the second ferroelectric material on the second side.

15. The memory device of claim 12, wherein a second bias changes a polarization of the first ferroelectric material on the first side and a polarization of the second ferroelectric material on the second side.

16. The memory device of claim 12, wherein a dielectric material separates the first ferroelectric material on the first side and the second ferroelectric material on the second side of the via.

17. A memory device, comprising:

a first ferroelectric material formed on an interior sidewall of a via and having a first thickness; and

a second ferroelectric material formed on an exterior sidewall of the via and having a second thickness; and

wherein the first ferroelectric material and the second ferroelectric material;

are separated by a conductive material; and

have a different coercive field.

18. The memory device of claim 17, wherein the first ferroelectric material is different than the second ferroelectric material.

19. The memory device of claim 17, wherein a polarization of the first ferroelectric material and a polarization of the second ferroelectric material are utilized to provide at least four distinct states of the memory device.

20. The memory device of claim 19, wherein each of the at least four distinct states stores a charge equivalent to a single bit DRAM cell charge.

21. A method of writing data to a multi-bit ferroelectric memory device, comprising:

assigning a state to each of a number of polarization combinations between a first ferroelectric material and a second ferroelectric material; and

wherein;

the first ferroelectric material is formed on an interior sidewall of a via and has a first thickness;

the second ferroelectric material is formed on an exterior sidewall of the via and has a second thickness; and

each of the number of polarization combinations corresponds to a particular applied bias.

22. The method of claim 21, comprising reassigning at least one state for at least one of the number of polarization combinations.

23. The method of claim 21, comprising applying the particular bias to the first ferroelectric material and to the second ferroelectric material to produce at least two polarization directions for the first ferroelectric material and for the second ferroelectric material.

24. The method of claim 21, comprising applying a first bias in a first direction to change a polarization direction of the first ferroelectric material without changing a polarization direction of the second ferroelectric material.

25. The method of claim 21, wherein the number of polarization combinations include a combination of a polarization direction of the first ferroelectric material and a polarization direction of the second ferroelectric material.

26. The method of claim 21, wherein assigning the state to each of the number of polarization combinations includes assigning the state to a number of biases.

27. The method of claim 26, comprising applying a bias to produce a distinct polarization combination between the first ferroelectric material and the second ferroelectric material.

28. The method of claim 21, wherein each state can be independently written by providing the corresponding bias of a particular assigned state.

29. A method of writing data to a multi-bit ferroelectric memory device, comprising:

defining a first state of the multi-bit ferroelectric memory device, wherein the first state includes applying a first bias in a first direction to the multi-bit ferroelectric memory device;

applying a second bias to the multi-bit ferroelectric memory device to generate a second state, wherein applying the second bias includes applying a second voltage in a second direction;

applying a third bias to the multi-bit ferroelectric memory device to generate a third state, wherein applying the third bias includes applying a third voltage that is greater than the second voltage in a second direction; and

applying a fourth bias to the multi-bit ferroelectric memory device to generate a fourth state, wherein applying the fourth bias includes applying a fourth voltage that is less than the third voltage in the second direction;

wherein the multi-bit ferroelectric memory device includes;

a first ferroelectric material formed on an interior sidewall of a via and having a first thickness; and

a second ferroelectric material formed on an exterior sidewall of the via and having a second thickness.

30. The method of claim 29, wherein applying each bias releases a different voltage to a bit line within a memory array.