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Systems and methods for clock path single-ended DCD and skew correction

  • US 9,219,470 B1
  • Filed: 04/30/2013
  • Issued: 12/22/2015
  • Est. Priority Date: 04/30/2013
  • Status: Active Grant
First Claim
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1. A circuit for improving signal integrity characteristics of a non-full rate transmitter, the circuit comprising:

  • an actuator block having an input for receiving a differential clock signal, the differential clock signal comprising a positive clock signal and a negative clock signal, the actuator configured to adjust a difference between the positive and negative clock signals;

    a sensing block, for sensing a difference between positive and negative signals of a differential signal, the differential signal being related to the clock signal, the sensing block comprising;

    a plurality of different types of sensors; and

    at least one switch for selecting between the plurality of different types of sensors; and

    a calibration block for providing a control signal to the actuator based on the sensed difference between the positive and negative signals.

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