Systems and methods for clock path single-ended DCD and skew correction

• US 9,219,470 B1
• Filed: 04/30/2013
• Issued: 12/22/2015
• Est. Priority Date: 04/30/2013
• Status: Active Grant

• Current Assignee: Microsemi Solutions (U.S.), Inc. (Microchip Technology Incorporated)
• Original Assignee: PMC Sierra US Inc (Microchip Technology Incorporated)
• Inventors: Venditti, Michael Ben
• Primary Examiner(s): TRAN, VINCENT HUY
• Application Number:
  US13/873,817
• Time in Patent Office: 966 Days
• Field of Search: 713/503, 375/375, 375/355, 375/226, 375/276
• US Class Current: 1/1
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

A circuit and method for improving signal integrity characteristics of a non-full rate transmitter are disclosed herein. The circuit comprises an actuator block having an input for receiving a differential clock signal, the differential clock signal comprising a positive clock signal and a negative clock signal, the actuator configured to adjust a difference between the positive and negative clock signals; a sensing block, for sensing a difference between positive and negative signals of a differential signal, the differential signal being related to the clock signal; and a calibration block for providing a control signal to the actuator based on the sensed difference between the positive and negative signals.

Claims

1. A circuit for improving signal integrity characteristics of a non-full rate transmitter, the circuit comprising:

an actuator block having an input for receiving a differential clock signal, the differential clock signal comprising a positive clock signal and a negative clock signal, the actuator configured to adjust a difference between the positive and negative clock signals;

a sensing block, for sensing a difference between positive and negative signals of a differential signal, the differential signal being related to the clock signal, the sensing block comprising;

a plurality of different types of sensors; and

at least one switch for selecting between the plurality of different types of sensors; and

a calibration block for providing a control signal to the actuator based on the sensed difference between the positive and negative signals.

2. The circuit of claim 1, wherein the differential signal comprises a differential clock signal.

3. The circuit of claim 2, wherein the sensing block comprises a clock skew sensor.

4. The circuit of claim 2, wherein the circuit is configured to correct clock polarity skew.

5. The circuit of claim 1, wherein the differential signal comprises a differential output signal of the non-full rate transmitter.

6. The circuit of claim 5, wherein the circuit is configured to reduce EMI.

7. The circuit of claim 1, further comprising a comparison block configured to:

digitize the sensed difference between the adjusted positive and negative signals; and

provide the digitized sensed difference to the calibration block.

8. The circuit of claim 1, wherein the sensing block comprises a single ended duty cycle distortion (DCD) sensor.

9. The circuit of claim 1, wherein the sensing block comprises an RC filter.

10. The circuit of claim 1, wherein the sensing block comprises a DCD-free clock generator.

11. The circuit of claim 1, wherein the actuator block is configured to delay transitions of at least one of the positive signal and the negative signal.

12. The circuit of claim 1, wherein the actuator block is configured to advance transitions of at least one of the positive signal and the negative signal.

13. The circuit of claim 1, wherein the actuator block comprises an actuator having a current starved inverter.

14. The circuit of claim 13, wherein the actuator block comprises a plurality of parallel current starved inverters.

15. The circuit of claim 13, wherein the current starved inverter comprises an input for receiving an analog control signal.

16. The circuit of claim 13, wherein the current starved inverter comprises an input for receiving a digital control signal.

17. The circuit of claim 1, wherein the circuit is configured to correct differential DCD.

18. The circuit of claim 1, wherein the circuit is configured to correct single-ended DCD.

19. The circuit of claim 1, wherein the non-full rate transmitter comprises a half rate transmitter.

20. The circuit of claim 1, wherein the non-full rate transmitter comprises a quarter rate transmitter.