Computationally efficient convolutional coding with rate-matching

• US 9,219,502 B2
• Filed: 01/26/2015
• Issued: 12/22/2015
• Est. Priority Date: 06/08/2007
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Cheng, Jung-Fu
• Primary Examiner(s): Chase, Shelly A
• Application Number:
  US14/605,922
• Publication Number:
  US 20150143207A1
• Time in Patent Office: 330 Days
• US Class Current: 1/1
• CPC Class Codes: H03M 13/23 using convolutional codes, e.g. unit memory codes
• CPC Class Codes: H03M 13/235 Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/2732 Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver
• CPC Class Codes: H03M 13/2792 Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/6356 by repetition or insertion of dummy data, i.e. rate reduction
• CPC Class Codes: H03M 13/6362 by puncturing
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/0069 Puncturing patterns
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.

Claims

1. A communication terminal for a mobile communications system, comprising,

an error coding circuit, the error coding circuit further comprised of:

a convolutional encoder configured to receive an input bit stream and to generate two or more groups of parity bits from the input bit stream;

an interleaver circuit configured to separately interleave parity bits within each group of parity bits; and

a rate-matching circuit configured to output a selected number of said interleaved parity bits, to obtain an output code rate, such that a first one of the groups is output before a second one of the groups.

2. The communication terminal of claim 1, wherein the rate-matching circuit includes a circular buffer storing the interleaved parity bits, ordered by group, and wherein said rate-matching circuit is configured to output the selected number of interleaved parity bits from the circular buffer.

3. The communication terminal of claim 1, wherein said interleaver circuit is configured to apply identical interleaving for each group of parity bits.

4. The communication terminal of claim 1, wherein the rate-matching circuit is configured to puncture parity bits, when the two or more groups of parity bits include more bits than needed to achieve the output code rate, by puncturing up to all of the parity bits in one of the groups of parity bits before puncturing bits in any other group of parity bits.

5. The communication terminal of claim 1, wherein the rate-matching circuit is configured to repeat parity bits, when the two or more groups of parity bits include fewer bits than needed to achieve the output code rate, by repeating up to all of the parity bits in one of the groups of parity bits before repeating bits in any other group of parity bits.