Adaptive delay base loss equalization

• US 9,219,623 B2
• Filed: 09/30/2004
• Issued: 12/22/2015
• Est. Priority Date: 09/30/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: McCall, James A., Ruff, Klaus, Shykind, David, Chaudhuri, Santanu
• Primary Examiner(s): Joseph, Jaison
• Application Number:
  US10/956,426
• Publication Number:
  US 20060067398A1
• Time in Patent Office: 4,100 Days
• Field of Search: 375/229, 375/232, 375/236
• US Class Current: 1/1
• CPC Class Codes: H04L 2025/03751 only once, at installation H04L2025/03738 takes precedence
• CPC Class Codes: H04L 25/0224 using sounding signals
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A method, system and apparatus to self-determine equalization parameters for a channel. An initiator sends an equalization insensitive signal (EIS) to a responder on channel to be equalized and begins a count. A responder responds with an EIS. When the initiator receives the response EIS the count is terminated. The count, which constitutes a measure of delay in the channel, may be used to determine desirable equalization parameters for the channel.

Claims

1. A system comprising:

a motherboard;

.

a processor to self-determine an equalization parameter for a first channel on which the processor communicates, the processor coupled to the motherboard;

a chipset coupled to the motherboard, the motherboard defining the first channel between the chipset and the processor;

a memory coupled to the motherboard; and

the motherboard defining a second channel between the memory and the chipset.

2. The system of claim 1 wherein the chipset comprises:

logic to self-determine an equalization parameter for the second channel.

3. The system of claim 1 wherein the processor and the chipset each comprise:

a signal generator to generate an equalization insensitive signal; and

a counter to determine a delay from transmission of the equalization insensitive signal to receipt of a response signal.

4. The system of claim 1 wherein the processor comprises:

logic to determine a round trip signal delay on the first channel; and

a lookup table indexed by the delay to identify the equalization parameter.

5. The system of claim 1 wherein the first channel comprises:

a plurality of link elements of different lengths and wherein the equalization parameter is determined from a delay on the longest link element of the channel.