Switch, information processing apparatus, and communication control method

• US 9,219,695 B2
• Filed: 12/20/2012
• Issued: 12/22/2015
• Est. Priority Date: 03/29/2012
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Sato, Mitsuru
• Primary Examiner(s): Huynh, Dung B
• Application Number:
  US13/721,127
• Publication Number:
  US 20130259053A1
• Time in Patent Office: 1,097 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/382 using universal interface adapter
• CPC Class Codes: G06F 3/00 Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags

Abstract

A PCIe switch stores therein a first identifier used by a CPU to identify a device, a second identifier that is a common identifier to identify the device in a network formed among a plurality of switches that connect the CPU to the device, and a destination of an access request to the device in an associated manner. When having received an access request from the CPU, the PCIe switch identifies a second identifier and a destination that are associated with a first identifier included in the access request. After that, the PCIe switch adds the identified second identifier to the access request, and transmits the access request with the second identifier added to the identified destination.

Claims

1. A switch comprising:

a memory; and

a processor coupled to the memory, wherein the processor executes a process comprising;

storing, in the memory, a first identifier used by a Central Processing Unit (CPU) that accesses a device using Peripheral Component Interconnect (PCI) Express to identify the device, a second identifier that is a common identifier to identify the device in a network formed among a plurality of switches that connect the CPU to the device, and a destination of an access request to the device in an associated manner;

identifying, when the switch has received the access request from the CPU, the second identifier and the destination that are associated with the first identifier included in the access request in the memory;

adding the second identifier identified at the identifying to the access request, the adding writes the second identifier identified at the identifying in a Transaction Layer Packet (TLP) prefix area of the PCI Express in the access request transmitted from the CPU using the PCI Express;

when the destination identified at the identifying is another switch, transmitting the access request with the second identifier to the destination identified at the identifying; and

when the destination identified at the identifying is the device, deleting the second identifier from the access request and transmitting the access request with no second identifier.

2. The switch according to claim 1, wherein

when the second identifier is included in the access request received from another switch, the identifying identifies the destination associated with the second identifier in the memory, and

the transmission transmits the received access request to the destination identified at the identifying.

3. The switch according to claim 1, wherein the processor executes a process further comprising changing, when the switch has received an instruction to change the destination stored in the memory from a management server that manages the switch, the destination stored in the memory to specified content.

4. An information processing apparatus comprising:

a memory; and

a processor coupled to the memory, wherein the processor executes a process comprising;

storing, in the memory, a first identifier used by a Central Processing Unit (CPU) that accesses a device using Peripheral Component Interconnect (PCI) Express to identify the device, a second identifier that is a common identifier to identify the device in a network formed among a plurality of switches that connect the CPU to the device, and a destination of an access request to the device in an associated manner;

identifying, when the information processing apparatus has received the access request from the CPU, the second identifier and the destination that are associated with the first identifier included in the access request in the memory;

adding the second identifier identified at the identifying to the access request, the adding writes the second identifier identified at the identifying in a Transaction Layer Packet (TLP) prefix area of the PCI Express in the access request transmitted from the CPU using the PCI Express;

when the destination identified at the identifying is another switch, transmitting the access request with the second identifier to the destination identified at the identifying; and

when the destination identified at the identifying is the device, deleting the second identifier from the access request and transmitting the access request with no second identifier.

5. A communication control method comprising:

receiving, by an apparatus, an access request from a Central Processing Unit (CPU);

identifying, by the apparatus, a second identifier and a destination that are associated with a first identifier included in the access request with reference to a memory that stores therein the first identifier used by the CPU that accesses a device using Peripheral Component Interconnect (PCI) Express to identify the device, the second identifier that is a common identifier to identify the device in a network formed among a plurality of switches that connect the CPU to the device, and the destination of an access request to the device in an associated manner;

adding, by the apparatus, the identified second identifier to the access request, the adding writes the second identifier identified at the identifying in a Transaction Layer Packet (TLP) prefix area of the PCI Express in the access request transmitted from the CPU using the PCI Express;

when the destination identified at the identifying is another switch, transmitting, by the apparatus, the access request with the second identifier added to the identified destination; and

when the destination identified at the identifying is the device, deleting, by the apparatus, the second identifier from the access request and transmitting, by the apparatus, the access request with no second identifier.