Multicore processor and onboard electronic control unit using same

• US 9,222,430 B2
• Filed: 01/03/2011
• Issued: 12/29/2015
• Est. Priority Date: 02/01/2010
• Status: Active Grant

• Current Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Wakabayashi, Tetsuaki, Arai, Soichiro
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): KINSEY, BRANDON MICHAEL
• Application Number:
  US12/983,487
• Publication Number:
  US 20110191620A1
• Time in Patent Office: 1,821 Days
• Field of Search: 713/322, 713/500
• US Class Current: 1/1
• CPC Class Codes: F02D 41/26 using computer, e.g. microprocessor
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multicore processor according to the invention has a plurality of cores. The plurality of cores are configured to operate at an operation clock with a frequency varying periodically with the same period, and a variation phase of a frequency of the operation clock of each core of the plurality of cores is shifted by a predetermined amount among the plurality of cores.

Claims

1. A multicore processor comprising:

a plurality of cores, wherein;

the plurality of cores are configured to each operate at an operation clock, each operation clock having a frequency varying cyclically, wherein periods of the cyclic variations are the same; and

a variation phase of the frequency of the operation clock of each core of the plurality of cores is shifted by a predetermined amount, wherein the predetermined amount is the same among the plurality of cores.

2. The multicore processor according to claim 1, wherein:

the number of the plurality of cores is an integer and is equal to or greater than 2; and

the variation phase of the frequency of the operation clock of each core is shifted by a phase corresponding to a time that is obtained by dividing the period by the number of the plurality of cores.

3. The multicore processor according to claim 1, wherein:

a central frequency during the variations of a frequency of the operation clock of each core of the plurality of cores is the same among the plurality of cores; and

an amplitude of the frequency of the operation clock of each core of the plurality of cores is the same among the plurality of cores.

4. The multicore processor according to claim 1, wherein a variation mode of the frequency of the operation clock of each core of the plurality of cores is the same among the plurality of cores.

5. The multicore processor according to claim 1, wherein a shift amount of the variation phase of the frequency of the operation clock among the cores during operation is changed in accordance with an operational condition of the plurality of cores.

7. The multicore processor according to claim 1, wherein the frequency of the operation clock of each core is set to vary cyclically within a predetermined range around a particular frequency.

8. The multicore processor according to claim 7, wherein the predetermined range is ±

1 MHz.

9. The multicore processor according to claim 8, wherein the particular frequency is 100 MHz.

10. The multicore processor according to claim 1, wherein the frequency of the operation clock of each core is set to vary sinusoidally within a predetermined range around a center frequency.

11. The multicore processor according to claim 10, wherein the predetermined range is ±

1 MHz.

12. The multicore processor according to claim 11, wherein the center frequency is 100 MHz.

6. An onboard electronic control unit comprising:

a multicore processor having a plurality of cores, wherein

the plurality of cores are each configured to operate at an operation clock, each operation clock having a frequency varying cyclically, wherein periods of the cyclic variations are the same, and

a variation phase of the frequency of the operation clock of each core of the plurality of cores is shifted by a predetermined amount, wherein the predetermined amount is the same among the plurality of cores.