Integrated driver and related method

• US 9,223,153 B2
• Filed: 06/30/2015
• Issued: 12/29/2015
• Est. Priority Date: 12/01/2010
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Zuffada, Maurizio, Pozzoni, Massimo, Contini, Angelo
• Primary Examiner(s): Kianni, Kaveh C
• Application Number:
  US14/788,724
• Publication Number:
  US 20150301362A1
• Time in Patent Office: 182 Days
• Field of Search: 385/3, 385/14
• US Class Current: 1/1
• CPC Class Codes: G02B 2006/12142 Modulator
• CPC Class Codes: G02B 2006/12145 Switch
• CPC Class Codes: G02B 6/1225 comprising photonic band-gap structures or photonic lattices
• CPC Class Codes: G02F 1/0121 Operation of devices; Circuit arrangements, not otherwise provided for in this subclass
• CPC Class Codes: G02F 1/0327 Operation of the cell; Circuit arrangements G02F1/05 takes precedence
• CPC Class Codes: G02F 1/212 Mach-Zehnder type
• CPC Class Codes: G02F 1/225 in an optical waveguide structure
• CPC Class Codes: H03F 1/22 by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2200/45 the load of the amplifier being a capacitive element, e.g. CRT
• CPC Class Codes: H03F 2200/516 Some amplifier stages of an amplifier use supply voltages of different value
• CPC Class Codes: H03F 2203/30099 the pull transistor being gated by a switching element
• CPC Class Codes: H03F 2203/30132 the push transistor being gated by a switching element
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/3001 with field-effect transistors
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H04B 10/532 Polarisation modulation
• CPC Class Codes: H04B 10/616 : Details of the electronic signal processing in coherent optical receivers

Abstract

A driver circuit may include a first node, and a first circuit to generate on the first node an inverted replica of an input signal during driver switching between a first supply voltage and a first reference voltage, the inverted replica having a threshold voltage value based upon a second reference voltage greater than the first supply voltage. The driver circuit may include a cascode stage to be controlled by the second reference voltage and to be coupled between a second supply voltage and the first node, a delay circuit to generate a delayed replica of the input signal, an amplifier, and a switching network to couple the control terminal of the active load transistor to one of the first reference voltage and the first node based upon the input signal.

Claims

1. A method of generating an output signal switching between a second supply voltage and a first reference voltage, starting from an input signal switching between a first supply voltage and the first reference voltage using an amplifier, the amplifier having a first switch to be coupled to the first reference voltage and to be controlled by a delayed replica of the input signal, a second switch to be controlled by the first supply voltage and comprising a conduction terminal to define an output terminal, and an active load switch to be coupled between the output terminal and the second supply voltage and comprising a control terminal, the method comprising:

generating an inverted replica of the input signal having a threshold voltage based upon a second reference voltage greater than the first supply voltage;

controlling the first switch with the delayed replica of the input signal;

controlling the second switch with the first supply voltage; and

coupling the control node of the active load switch to at least one of the first reference voltage and the inverted replica of the input signal based upon on a level of the input signal.

2. The method of claim 1 wherein the input signal comprises a square-wave input signal;

and wherein the output signal comprises a square-wave output signal.

3. The method of claim 1 wherein the conduction terminal of the second switch is not in common with the first switch.

4. The method of claim 1 wherein the active load switch comprises a high-voltage active load switch.

5. A method of operating a driver circuit comprising:

generating on a first node an inverted replica of an input signal during driver switching between a first supply voltage and a first reference voltage, the inverted replica having a threshold voltage value based upon a second reference voltage greater than the first supply voltage;

operating a cascode stage controlled by the second reference voltage and coupled between a second supply voltage and said first node;

generating a delayed replica of the input signal;

operating an amplifier comprising

a first switch coupled to the first reference voltage and controlled by the delayed replica of the input signal,

a second switch controlled by the first supply voltage and comprising a conduction terminal to define an output terminal, and

an active load switch coupled between the output terminal and the second supply voltage and comprising a control terminal; and

coupling said control terminal of said active load switch to at least one of the first reference voltage and said first node based upon the input signal.

6. The method of claim 5 wherein the input signal comprises a square-wave input signal;

and wherein coupling said control terminal of said active load switch is based upon a level of the square-wave input signal.

7. The method of claim 5 wherein generating on the first node the inverted replica comprises:

inverting the input signal using a plurality of switches having a common node; and

operating a boost capacitor coupled between said common node of said plurality of switches and said first node to be charged at a voltage to keep said cascode stage in a functioning mode.

8. The method of claim 5 wherein generating the delayed replica comprises generates the delayed replica to turn on said first switch after said active load switch has turned off.

9. The method of claim 5 wherein said first switch, and said second switch, each comprises a low-voltage metal-oxide-semiconductor field-effect transistor (MOSFET).

10. The method of claim 5 wherein said conduction terminal of said second switch is not in common with said first switch.

11. The method of claim 5 wherein said active load switch comprises a high-voltage active load switch.

12. The method of claim 5 wherein said amplifier comprises a class AB amplifier.

13. A method of controlling a Mach-Zender optical modulator comprising:

generating on a first node an inverted replica of an input signal during driver switching between a first supply voltage and a first reference voltage, the inverted replica having a threshold voltage value based upon a second reference voltage greater than the first supply voltage;

operating a cascode stage controlled by the second reference voltage and coupled between a second supply voltage and said first node;

generating a delayed replica of the input signal;

operating an amplifier comprising

a first switch coupled to the first reference voltage and controlled by the delayed replica of the input signal,

a second switch controlled by the first supply voltage and comprising a conduction terminal to define an output terminal coupled to the Mach-Zender optical modulator, and

an active load switch coupled between the output terminal and the second supply voltage and comprising a control terminal; and

coupling said control terminal of said active load switch to at least one of the first reference voltage and said first node based upon the input signal.

14. The method of claim 13 wherein the input signal comprises a square-wave input signal;

and wherein coupling said control terminal of said active load switch is based upon a level of the square-wave input signal.

15. The method of claim 13 wherein generating on the first node the inverted replica comprises:

inverting the input signal using a plurality of switches having a common node; and

operating a boost capacitor coupled between said common node of said plurality of switches and said first node to be charged at a voltage to keep said cascode stage in a functioning mode.

16. The method of claim 13 wherein generating the delayed replica comprises generating the delayed replica to turn on said first switch after said active load switch has turned off.

17. The method of claim 13 wherein said first switch, and said second switch, each comprises a low-voltage metal-oxide-semiconductor field-effect transistor (MOSFET).

18. The method of claim 13 wherein said conduction terminal of said second switch is not in common with said first switch.

19. The method of claim 13 wherein said active load switch comprises a high-voltage active load switch.

20. The method of claim 13 wherein said amplifier comprises a class AB amplifier.