Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media
First Claim
1. A synthesized performance level setting circuit configured to synthesize an intermediate performance level for a functional block of an integrated circuit, the synthesized performance level setting circuit configured to:
- receive as input a performance mode input; and
responsive to receiving the performance mode input indicating a synthesized performance mode;
generate a power source selection output to select a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and generate a clock frequency setting output to select a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval; and
generate the power source selection output to select a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and generate the clock frequency setting output to select a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval;
receive as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a high performance mode; and
responsive to receiving the performance mode override input indicating the high performance mode;
generate the power source selection output to select the first power source to provide power to the functional block at the first voltage level, and generate the clock frequency setting output to select the first clock frequency associated with the first voltage level to clock the functional block.
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Accused Products
Abstract
Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a synthesized performance level setting circuit receives an input indicating a synthesized performance mode. The circuit generates a power source selection output to select a first power source providing power to an integrated circuit functional block at a first voltage level, and generate a clock frequency setting output to select a first clock frequency associated with the first voltage level to clock the functional block, for a first predefined time interval. The circuit also generates the power source selection output to select a second power source to provide power at a second voltage level lower than the first voltage level, and generate the clock frequency setting output to select a second clock frequency associated with the second voltage level to clock the functional block, for a second predefined time interval.
13 Citations
42 Claims
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1. A synthesized performance level setting circuit configured to synthesize an intermediate performance level for a functional block of an integrated circuit, the synthesized performance level setting circuit configured to:
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receive as input a performance mode input; and responsive to receiving the performance mode input indicating a synthesized performance mode; generate a power source selection output to select a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and generate a clock frequency setting output to select a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval; and generate the power source selection output to select a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and generate the clock frequency setting output to select a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval; receive as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a high performance mode; and responsive to receiving the performance mode override input indicating the high performance mode; generate the power source selection output to select the first power source to provide power to the functional block at the first voltage level, and generate the clock frequency setting output to select the first clock frequency associated with the first voltage level to clock the functional block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A synthesized performance level setting circuit configured to synthesize an intermediate performance level for a functional block of an integrated circuit, the synthesized performance level setting circuit comprising:
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a means for receiving as input a performance mode input; a means for determining that the performance mode input indicates a synthesized performance mode; a means for selecting a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and selecting a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval, responsive to a determination that the performance mode input indicates the synthesized performance mode; a means for selecting a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and selecting a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval, responsive to the determination that the performance mode input indicates the synthesized performance mode; a means for receiving a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a high performance mode; and a means for generating a power source selection output to select the first power source to provide power to the functional block at the first voltage level, and generating a clock frequency setting output to select the first clock frequency associated with the first voltage level to clock the functional block, responsive to receiving the performance mode override input indicating the high performance mode.
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14. A method for synthesizing an intermediate performance level for a functional block of an integrated circuit, comprising:
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receiving as input a performance mode input; and responsive to receiving the performance mode input indicating a synthesized performance mode; selecting a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and selecting a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval; and selecting a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and selecting a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval; receiving as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a high performance mode; and responsive to receiving the performance mode override input indicating the high performance mode; selecting the first power source to provide power to the functional block at the first voltage level, and selecting the first clock frequency associated with the first voltage level to clock the functional block. - View Dependent Claims (15, 16, 17, 18)
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19. A non-transitory computer-readable medium having stored thereon computer-executable instructions to cause a processor to implement a method for synthesizing an intermediate performance level for a functional block of an integrated circuit, the method comprising:
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receiving as input a performance mode input; and responsive to receiving the performance mode input indicating a synthesized performance mode; selecting a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and selecting a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval; and selecting a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and selecting a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval; receiving as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a high performance mode; and responsive to receiving the performance mode override input indicating the high performance mode; selecting the first power source to provide power to the functional block at the first voltage level, and selecting the first clock frequency associated with the first voltage level to clock the functional block. - View Dependent Claims (20, 21, 22, 23)
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24. A synthesized performance level setting circuit configured to synthesize an intermediate performance level for a functional block of an integrated circuit, the synthesized performance level setting circuit configured to:
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receive as input a performance mode input; and responsive to receiving the performance mode input indicating a synthesized performance mode; generate a power source selection output to select a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and generate a clock frequency setting output to select a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval; and generate the power source selection output to select a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and generate the clock frequency setting output to select a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval; receive as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a low performance mode; and responsive to receiving the performance mode override input indicating the low performance mode; generate the power source selection output to select the second power source to provide power to the functional block at the second voltage level lower than the first voltage level, and generate the clock frequency setting output to select the second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A synthesized performance level setting circuit configured to synthesize an intermediate performance level for a functional block of an integrated circuit, the synthesized performance level setting circuit comprising:
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a means for receiving as input a performance mode input; a means for determining that the performance mode input indicates a synthesized performance mode; a means for selecting a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and selecting a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval, responsive to a determination that the performance mode input indicates the synthesized performance mode; a means for selecting a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and selecting a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval, responsive to the determination that the performance mode input indicates the synthesized performance mode; a means for receiving as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a low performance mode; and a means for selecting the second power source to provide power to the functional block at the second voltage level lower than the first voltage level, and selecting the second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block, responsive to receiving the performance mode override input.
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35. A method for synthesizing an intermediate performance level for a functional block of an integrated circuit, comprising:
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receiving as input a performance mode input; and responsive to receiving the performance mode input indicating a synthesized performance mode; selecting a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and selecting a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval; and selecting a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and selecting a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval; receiving as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a low performance mode; and responsive to receiving the performance mode override input indicating the low performance mode; selecting the second power source to provide power to the functional block at the second voltage level lower than the first voltage level, and selecting the second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block. - View Dependent Claims (36, 37, 38, 41, 42)
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39. A non-transitory computer-readable medium having stored thereon computer-executable instructions to cause a processor to implement a method for synthesizing an intermediate performance level for a functional block of an integrated circuit, the method comprising:
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receiving as input a performance mode input; and responsive to receiving the performance mode input indicating a synthesized performance mode; selecting a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and selecting a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval; and selecting a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and selecting a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval; receiving as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a low performance mode; and responsive to receiving the performance mode override input indicating the low performance mode; selecting the second power source to provide power to the functional block at the second voltage level lower than the first voltage level, and selecting the second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block. - View Dependent Claims (40)
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Specification