System, method and computer program product for fetching data between an execution of a plurality of threads

• US 9,223,507 B1
• Filed: 01/05/2015
• Issued: 12/29/2015
• Est. Priority Date: 04/06/2011
• Status: Active Grant

• Current Assignee: P4tents1 LLC
• Original Assignee: P4tents1 LLC
• Inventors: Smith, Michael S
• Primary Examiner(s): Cardwell, Eric S
• Application Number:
  US14/589,937
• Time in Patent Office: 358 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0824 Distributed directories, e.g. linked lists of caches
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 2206/1014 One time programmable [OTP] memory, e.g. PROM, WORM
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 9/44557 Code layout in executable memory
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/4824 : Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, computer program product, and associated method/processing unit are provided for utilizing a memory subsystem including a first memory of a first memory class, and a second memory of a second memory class communicatively coupled to the first memory. In operation, data is fetched using a time between an execution of a plurality of threads.

Claims

1. An apparatus, comprising:

a memory sub-system including;

a first memory of a first memory class; and

a second memory of a second memory class, the second memory communicatively coupled to the first memory;

said memory sub-system configured for;

receiving, over a standard bus associated with a DDR protocol, a command including data of which at least a portion is used in connection with a corresponding command,

after the receipt of the command including the data of which the at least portion is used in connection the corresponding command, causing particular information in the first memory to be written to the second memory, and

after a status check in connection with the memory sub-system, receiving a read command to read the particular information written to the second memory;

wherein the apparatus is configured for writing the particular information to the second memory using a time between an execution of a plurality of threads.

2. An apparatus, comprising:

a plurality of memories including NAND flash memory and random access memory;

a first circuit for receiving DDR signals and outputting SATA signals, the first circuit capable of being communicatively coupled to a first bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; and

a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a second bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a third bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory;

said apparatus configured for;

receiving, at the first circuit via the first bus associated with the DDR protocol, a command including data of which at least a portion is used in connection with a corresponding command communicated over at least one of the second bus or the third bus;

after the receipt of the command, writing particular information that is in one of the plurality of memories to another one of the plurality of memories, utilizing the second circuit; and

providing a status in connection with the particular information.

3. The apparatus of claim 2, wherein the apparatus is configured such that an execution of at least one of a plurality of threads involves one of a plurality of commands that is required to be received from a processing unit utilizing the DDR protocol for initiating a random access data read from the NAND flash memory via the random access memory.

4. The apparatus of claim 3, wherein the apparatus is configured such that the execution of at least another one of the plurality of threads involves another one of the plurality of commands that is required to be received from the processing unit utilizing the DDR protocol for completing the random access data read from the NAND flash memory via the random access memory.

5. The apparatus of claim 2, wherein the apparatus is configured such that, after the receipt of the command but before the particular information that is in the one of the plurality of memories is written to the another one of the plurality of memories, the apparatus is configured for receiving and processing an additional command for initiating at least one of a random access read operation or a random access write operation.

6. The apparatus of claim 2, wherein the apparatus is configured such that, after the receipt of the command but before the status is provided, the apparatus is configured for receiving and processing an additional command for initiating at least one of a random access read operation or a random access write operation.

7. The apparatus of claim 2, wherein the apparatus is configured such that, after the receipt of the command but before a completion of at least one of a random access read operation or a random access write operation initiated by the command, the apparatus is configured for receiving and processing an additional command for initiating at least one of a subsequent random access read operation or a subsequent random access write operation.

8. The apparatus of claim 2, wherein the apparatus is configured such that the command causes at least a portion of a random access data read.

9. The apparatus of claim 8, wherein the apparatus is configured such that the random access data read is one of a plurality of random access reads interspersed with a plurality of random access writes.

10. The apparatus of claim 8, wherein the apparatus is configured such that the random access data read is one of a plurality of random access reads interleaved with a plurality of random access writes performed in real-time.

11. The apparatus of claim 8, wherein the apparatus is configured such that the random access data read includes an arbitrary access data read.

12. The apparatus of claim 8, wherein the apparatus is configured such that the random access data read includes an access in connection with at least one of an arbitrary time or an arbitrary address.

13. The apparatus of claim 2, and further comprising an additional memory that is of a class that is different from at least one of the NAND flash memory or the random access memory.

14. The apparatus of claim 13, wherein the apparatus is configured such that the additional memory is of a class that is different from both the NAND flash memory and the random access memory.

15. The apparatus of claim 13, wherein the apparatus is configured such that the additional memory is part of the first circuit.

16. The apparatus of claim 13, and further comprising another additional memory that is of a class that is different from the additional memory.

17. The apparatus of claim 16, wherein the apparatus is configured such that the another additional memory is part of the first circuit.

18. The apparatus of claim 13, and further comprising another additional memory that is of a class that is different from the additional memory, the NAND flash memory, and the random access memory.

19. The apparatus of claim 13, wherein the apparatus is configured such that a random access data read from the NAND flash memory is carried out utilizing the additional memory.

20. The apparatus of claim 2, wherein the apparatus is configured such that the command is stored in logic memory.

21. The apparatus of claim 2, wherein the apparatus is configured such that at least a portion of the command is stored in logic memory in the first circuit.

22. The apparatus of claim 2, wherein the apparatus is configured such that at least a portion of the command is stored in at least one table in logic memory in the first circuit.

23. The apparatus of claim 2, wherein the apparatus is configured such that the first circuit provides the status.

24. The apparatus of claim 2, wherein the apparatus is configured such that the second circuit provides the status.

25. The apparatus of claim 2, wherein the apparatus is configured such that the status is provided via a status message.

26. The apparatus of claim 2, wherein the apparatus is configured such that the status is provided via a status bit.

27. The apparatus of claim 2, wherein the apparatus is configured such that the status is provided by being made accessible to a source of the command.

28. The apparatus of claim 27, wherein the apparatus is configured such that the source of the command includes a central processing unit.

29. The apparatus of claim 2, wherein the apparatus is configured such that the status is in connection with the writing of the particular information.

30. The apparatus of claim 2, wherein the apparatus is configured such that the status is in connection with the writing of all of the particular information.

31. The apparatus of claim 30, wherein the apparatus is configured such that the status is in connection with the writing of all of the particular information to the NAND flash memory or the random access memory.

32. The apparatus of claim 30, wherein the apparatus is configured such that the status is in connection with the writing being complete.

33. The apparatus of claim 30, wherein the apparatus is configured such that the status is in connection with the writing of all of the particular information to additional intermediate memory.

34. The apparatus of claim 2, wherein the apparatus is configured such that the status is provided in the form of a response that is communicated at an arbitrary time.

35. The apparatus of claim 2, wherein the apparatus is configured such that the status is provided in the form of a response to a status query.

36. The apparatus of claim 2, wherein the apparatus is configured such that the command includes a write command for causing a random access data write operation.

37. The apparatus of claim 36, wherein the apparatus is configured such that the status is in connection with the random access data write operation involving the particular information.

38. The apparatus of claim 2, wherein the apparatus is configured such that the command includes a read command for causing a random access data read operation.

39. The apparatus of claim 38, wherein the apparatus is configured such that the status is in connection with the random access data read operation involving the particular information.

40. The apparatus of claim 2, wherein the apparatus is configured such that the command is capable of being addressed to a particular memory location.

41. The apparatus of claim 40, wherein the apparatus is configured such that the particular memory location includes a predetermined particular memory location.

42. The apparatus of claim 40, wherein the apparatus is configured such that the particular memory location includes a special memory location.

43. The apparatus of claim 40, wherein the apparatus is configured such that the particular memory location is incapable of being subject of standard addressing under the DDR protocol.

44. The apparatus of claim 40, wherein the apparatus is configured such that the particular memory location is capable of standard addressing under a specification of a JEDEC standard, but is also capable of being used in a way that is undescribed in the specification of the JEDEC standard.

45. The apparatus of claim 40, wherein the apparatus is configured such that the particular information that is in the one of the plurality of memories is caused to be written to the another one of the plurality of memories, based at least in part on the command being addressed to the particular memory location.

46. The apparatus of claim 40, wherein the apparatus is configured such that the particular information that is in the one of the plurality of memories is caused to be written to the another one of the plurality of memories, based on the command being addressed to the particular memory location.

47. The apparatus of claim 40, wherein the apparatus is configured such that the command is capable of being addressed to the particular memory location for allowing communication of control to the apparatus.

48. The apparatus of claim 2, wherein the apparatus is configured such that the command is one of a plurality of commands that allow an input of control via the first bus associated with the DDR protocol, the plurality of commands further including at least one additional command that is capable of being addressed to a particular random access memory location, that is capable of standard addressing under a specification of a JEDEC standard but is also capable of being used in a way that is undescribed in the specification of the JEDEC standard, for allowing the input of the control via the first bus associated with the DDR protocol.

49. The apparatus of claim 2, wherein the apparatus is configured such that the status in connection with the particular information includes an availability status of the particular information.

50. The apparatus of claim 2, wherein the apparatus is configured such that the one of the plurality of memories includes the NAND flash memory and the another one of the plurality of memories includes the random access memory.

51. The apparatus of claim 2, wherein the apparatus is configured such that the one of the plurality of memories includes the random access memory and the another one of the plurality of memories includes the NAND flash memory.

52. The apparatus of claim 2, wherein the apparatus is configured such that the first circuit causes the particular information in the one of the plurality of memories to be written to the another one of the plurality of memories, by sending a standard command to the second circuit.

53. The apparatus of claim 2, wherein the apparatus is configured such that the DDR signals, the SATA signals, and the NAND flash signals are logical signals.

54. The apparatus of claim 2, wherein the apparatus is configured such that the particular information includes one or more pages.

55. The apparatus of claim 2, wherein the apparatus is configured such that the particular information includes at least a part of a memory page.

56. The apparatus of claim 2, wherein the apparatus is configured such that the first bus includes at least one of a DDR3 bus or a DDR4 bus.

57. The apparatus of claim 2, wherein the apparatus is configured such that the random access memory is part of the first circuit.

58. The apparatus of claim 2, wherein the apparatus is configured such that the random access memory is part of the second circuit.

59. The apparatus of claim 2, wherein the apparatus is configured such that the first circuit is operable for converting the DDR signals to the SATA signals.

60. The apparatus of claim 2, wherein the apparatus is configured such that the second circuit is operable for converting the SATA signals to the NAND flash signals.

61. The apparatus of claim 2, wherein the apparatus is configured such that the second bus includes a SATA bus and the third bus includes a NAND flash bus.

62. The apparatus of claim 2, wherein the apparatus is configured such that the command results in a plurality of SATA-related commands to be communicated via the second bus associated with the SATA protocol.

63. The apparatus of claim 2, wherein the apparatus is configured such that the command results in a plurality of NAND-related commands to be communicated via the third bus associated with the NAND flash protocol.

64. The apparatus of claim 2, wherein the apparatus is configured such that the first bus, the second bus, and the third bus are memory buses.

65. The apparatus of claim 2, wherein the random access memory includes static random access memory.

66. The apparatus of claim 2, wherein the random access memory includes dynamic random access memory.

67. The apparatus of claim 2, wherein the random access memory includes embedded random access memory.

68. The apparatus of claim 2, wherein the apparatus is configured such that the command and the status are each one or more of the DDR signals.

69. The apparatus of claim 2, wherein the apparatus is configured such that the particular information that is in the one of the plurality of memories is caused to be written to the another one of the plurality of memories, based at least in part on the command including the data of which the at least portion is used in connection the corresponding command communicated over at least one of the second bus or the third bus.

70. The apparatus of claim 2, wherein the apparatus is configured such that the particular information that is in the one of the plurality of memories is caused to be written to the another one of the plurality of memories, based on the command including the data of which the at least portion is used in connection the corresponding command communicated over at least one of the second bus or the third bus.

71. The apparatus of claim 2, wherein the apparatus is configured such that the corresponding command causes the particular information that is in the one of the plurality of memories to be written to the another one of the plurality of memories.

72. The apparatus of claim 2, wherein the apparatus is configured such that the corresponding command is sent over the second bus to cause the particular information that is in the one of the plurality of memories to be written to the another one of the plurality of memories.

73. The apparatus of claim 2, wherein the apparatus is configured such that the corresponding command is sent over the third bus to cause the particular information that is in the one of the plurality of memories to be written to the another one of the plurality of memories.

74. The apparatus of claim 2, wherein the apparatus is configured such that the command including the data works in combination with the corresponding command to cause the particular information that is in the one of the plurality of memories to be written to the another one of the plurality of memories.

75. The apparatus of claim 2, wherein the apparatus is configured such that the at least portion of the data is used in connection with the corresponding command, by the at least portion of the data being used to generate the corresponding command.

76. The apparatus of claim 2, wherein the apparatus is configured such that the at least portion of the data is used in connection with the corresponding command, by the at least portion of the data being used to generate corresponding data associated with the corresponding command.

77. The apparatus of claim 2, wherein the apparatus is configured such that the at least portion of the data is used in connection with the corresponding command, by the at least portion of the data being used to generate corresponding data included with the corresponding command.

78. The apparatus of claim 2, wherein the apparatus is configured such that the corresponding command includes at least part of the at least portion of the data.

79. The apparatus of claim 2, wherein the apparatus is configured such that the corresponding command is generated as a result of a protocol conversion.

80. The apparatus of claim 2, wherein the apparatus is configured such that a usage of the command allows control to be communicated over the first bus.

81. The apparatus of claim 2, wherein the apparatus is configured such that the particular information is written in response to a write command combined with the command including the data.

82. The apparatus of claim 2, wherein the apparatus is configured such that the particular information is written based on both a write command and the command including the data, which are discrete commands.

83. The apparatus of claim 2, wherein the apparatus is configured such that all of the data is used in connection with the corresponding command.

84. A computer program product embodied on a non-transitory computer readable medium, comprising:

a driver for controlling at least one processor to cooperate with a memory sub-system including;

a plurality of memories including NAND flash memory and random access memory;

a first circuit for receiving DDR signals via a first bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol;

the second circuit further for outputting SATA signals; and

a second circuit for receiving the SATA signals via a second bus associated with a SATA protocol, the second circuit further for outputting NAND flash signals via a third bus associated with a NAND flash protocol;

said driver configured to cause the at least one processor to;

send, to the first circuit via the first bus associated with the DDR protocol, a command including data of which at least a portion is used in connection with a corresponding command communicated over at least one of the second bus or the third bus, for causing particular information that is in one of the plurality of memories to be available in another one of the plurality of memories; and

checking a status of the particular information.

85. An apparatus, comprising:

a plurality of memories including NAND flash memory and random access memory;

first means for receiving DDR signals via a first bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; and

second means for receiving SATA signals and outputting NAND flash signals;

said apparatus configured for;

receiving, via the first bus associated with the DDR protocol, a command including data of which at least a portion is used in connection with a corresponding command communicated over at least one of the second bus or the third bus;

after the receipt of the command, writing particular information that is in one of the plurality of memories to another one of the plurality of memories; and

providing a status in connection with the particular information.