External memory controller node

• US 9,223,520 B2
• Filed: 06/30/2014
• Issued: 12/29/2015
• Est. Priority Date: 11/22/2002
• Status: Active Grant

• Current Assignee: Cornami, Inc.
• Original Assignee: QST Holdings LLC
• Inventors: Furtek, Frederick Curtis, Master, Paul L.
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US14/319,629
• Publication Number:
  US 20140310450A1
• Time in Patent Office: 547 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: H04L 67/60 Scheduling or organising the servicing of application requests, e.g. requests for application data transmissions using the analysis and optimisation of the required network resources admission control or resource allocation H04L47/70

Abstract

A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.

Claims

1. A memory controller for a multi-node computing circuit, the computing circuit including multiple computational nodes and an interconnection network interconnecting the computational nodes to each other and to the memory controller, wherein the computational nodes are organized in clusters of computational nodes and wherein the interconnection network includes a hierarchy of crosspoint switches to facilitate communication between a computational node in one cluster with a computational node in another cluster, the computational nodes communicating via at least one service, the memory controller comprising:

a network interface allowing one of the plurality of nodes to communicate with the memory controller for a request via the at least one service, the at least one service including one or a group of;

a peek and poke service, a memory random access (MRA) service, a direct memory access (DMA) service, a point-to-point (PTP) service, a real-time input (RTI) service and a message service; and

a memory interface configured to access a memory to fulfill the request.

2. The memory controller of claim 1, wherein at least one of the computational nodes is a processor.

3. The memory controller of claim 1, wherein the computing circuit includes a data address generator that generates sequences of addresses for both reading from and writing to the memory by the computational nodes.

4. The memory controller of claim 3, wherein the sequences of addresses are selected based on a data address generator mode.

5. The memory controller of claim 3, further comprising a port, wherein the data address generator is configurable by parameters from the port to generate the sequence of addresses.

6. The memory controller of claim 1, wherein the memory controller allows multiple independent simultaneous requests for memory accesses by the computational nodes to the memory.

7. The memory controller of claim 1, wherein the memory controller includes a predefined number of memory channels and wherein the memory request is assigned to a corresponding memory channel of the predefined number of memory channels.

8. The memory controller of claim 7, wherein the memory controller is configured to allow requests sent over different channels of the plurality of memory channels to be processed in an order other than the order in which the requests are received by the memory controller.

9. A computing machine comprising:

a memory;

a plurality of computational nodes embodied in an integrated circuit, the plurality of computational nodes communicating with each other via a service, each of the plurality of nodes configured to make requests for memory accesses to the memory via the service, at least two of the computational nodes being heterogeneous from each other;

an interconnection network coupled to the memory and the plurality of computational nodes, the interconnection network embodied in the integrated circuit; and

a memory controller coupled to the interconnection network and configured to receive requests for memory accesses by the computational nodes to the memory via the service, and

wherein the computational nodes are organized in clusters of computational nodes and wherein the interconnection network includes a hierarchy of crosspoint switches to facilitate communication between a computational node in one cluster with a computational node in another cluster.

10. The computing machine of claim 9, wherein at least one of the computational nodes is a processor.

11. The computing machine of claim 9, further comprising a data address generator that generates sequences of addresses for both reading from and writing to the memory by the computational nodes.

12. The computing machine of claim 11, wherein the sequences of addresses are selected based on a data address generator mode.

13. The computing machine of claim 11, wherein the memory controller includes a port, and wherein the data address generator is configurable by parameters from the port to generate the sequence of addresses.

14. The computing machine of claim 9, wherein the interconnection network includes a crosspoint switch.

15. The computing machine of claim 11, wherein the memory controller allows multiple independent simultaneous requests for memory accesses by the computational nodes to the memory.

16. The computing machine of claim 9, wherein the memory controller includes a predefined number of memory channels and wherein the memory request is assigned to a corresponding memory channel of the predefined number of memory channels.

17. The computing machine of claim 16, wherein the memory controller is configured to allow requests sent over different channels of the plurality of memory channels to be processed in an order other than the order in which the requests are received by the memory controller.