Apparatus and method for thread progress tracking

• US 9,223,615 B2
• Filed: 08/17/2012
• Issued: 12/29/2015
• Est. Priority Date: 10/12/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shin, Young Sam, Lee, Seung Won, Son, Min Young, Lee, Shi Hwa
• Primary Examiner(s): Patel, Hiren
• Application Number:
  US13/588,228
• Publication Number:
  US 20130097613A1
• Time in Patent Office: 1,229 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 2209/508 Monitor
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence

Abstract

Provided is a method and apparatus for measuring a progress or a performance of an application program in a computing environment using a micro-architecture. An apparatus for thread progress tracking may select a thread included in an application program, may determine, based on a predetermined criterion, whether an execution scheme for at least one instruction included in the thread corresponds to an effective execution scheme in which an execution time is uniform or a non-effective execution scheme in which a delayed cycle is included and the execution time is non-uniform, and may generate an effective progress index (EPI) by accumulating an execution time of an instruction executed by the effective execution scheme other than an instruction executed by the non-effective execution scheme.

Claims

1. An apparatus for thread progress tracking, the apparatus comprising:

a processor comprising;

a selector configured to select a thread included in an application program, wherein the thread includes a plurality of instructions;

a controller configured to determine, based on a predetermined criterion, an execution scheme for each instruction in the thread, wherein the execution scheme for each instruction on the thread is one of;

an effective execution scheme and a non-effective execution scheme, wherein the effective execution scheme has an execution time that is uniform, and wherein the non-effective execution scheme has a delayed cycle included and has an execution time that is non-uniform;

an effective progress counter (EPC) configured to generate an effective progress index (EPI) by accumulating an execution time of each instruction determined to have an effective execution scheme, and by not accumulating an execution time of each instruction determined to have a non-effective execution scheme; and

a kernel progress count (KPC) configured to generate a kernel progress index (KPI) by accumulating a cycle expended to operate a system kernel while the thread occupies a processor and the thread is executed, and by not accumulating an execution time of each instruction determined to have an effective execution scheme.

2. The apparatus of claim 1, wherein the non-effective execution scheme includes at least one of:

a hardware non-effective execution (HWNE) scheme that executes an instruction by the non-effective execution scheme at an instruction level of a processor based on hardware; and

a software non-effective execution (SWNE) scheme that executes a function by the non-effective execution scheme at a function level including instructions based on software.

3. The apparatus of claim 1, further comprising:

a memory progress counter (MPC) to generate a memory progress index (MPI) by accumulating a cycle expended to access a shared memory while the thread occupies a processor and the thread is executed.

4. The apparatus of claim 1, further comprising:

an input-output progress counter (IOPC) to generate an input-output progress index (IOPI) by accumulating a cycle used for repeatedly verifying input and output states to execute an input-output code of input/output (I/O) data while the thread occupies a processor and the thread is executed.

5. The apparatus of claim 1, wherein the EPC performs a count based on a system clock in response to the execution scheme being determined to be the effective execution scheme.

6. The apparatus of claim 1, wherein an operation of the EPC is controlled by a Hardware non-execution (HWNE) signal that executes an instruction via the non-effective execution scheme at an instruction level of a processor based on hardware, or a Software non-execution (SWNE) signal that executes a function via the non-effective execution scheme at a function level including instructions based on software.

7. The apparatus of claim 6, wherein the HWNE signal is generated based on a stall signal occurring in a processor.

8. The apparatus of claim 6, wherein the SWNE signal is generated using an application programming interface (API) when executing a user function including instructions.

9. The apparatus of claim 1, wherein the EPC comprises a determining unit to determine to set an SWNE signal so as to prevent the EPC from operating when the thread is in a non-running state.

10. The apparatus of claim 9, wherein the determining unit sets the SWNE signal to prevent the EPC from operating in response to an interrupt occurring in the thread that is in a running state, and clears the SWNE signal so that the EPC operates in response to the thread being in a running state after performing an interrupt service routine.

11. The apparatus of claim 1, wherein the EPC is located in a processor unit.

12. The apparatus of claim 1, further comprising:

a memory to store an EPI corresponding to a thread for each thread; and

a copying unit to copy a current value of the EPC to be the EPI in the memory when the thread is in a running state.

13. The apparatus of claim 1, further comprising:

a copying unit to copy a value of the EPC to be the EPI in a memory at a point in time at which a first thread context-switches to a second thread; and

a loading unit to load the EPI copied in the memory to the EPC in response to the second thread context-switching back to the first thread.

14. The apparatus of claim 1, further comprising:

a set determining unit to determine whether a flag value set to indicate that a non-effective function is in use is set in a thread control block of the thread on a scheduler.

15. The apparatus of claim 14, wherein the set determining unit suspends the EPC by setting an SWNE signal when the flag value is set, and corrects an increment of an EPC not used for effectively executing code of a thread when the flag value fails to be set.

16. A method for thread progress tracking, the method comprising:

selecting a thread included in an application program;

wherein the thread includes a plurality of instructions;

determining, based on a predetermined criterion, an execution scheme for each instruction in the thread, wherein the execution scheme for each instruction in the thread is one of;

an effective execution scheme and a non-effective execution scheme, wherein the effective execution scheme has an execution time that is uniform, and wherein the non-effective execution scheme has a delayed cycle included and has an execution time that is non-uniform;

generating an effective progress index (EPI) based on an effective progress counter (EPC) that accumulates an execution time of an instruction determined to have an effective execution scheme, and does not accumulate an execution time of each instruction determined to have a non-effective execution scheme; and

generating a kernel progress index (KPI) by accumulating a cycle expended to operate a system kernel while the thread occupies a processor and the thread is executed, and by not accumulating an execution time of each instruction determined to have an effective execution scheme.

17. The method of claim 16, wherein an operation of the EPC is controlled by a hardware non-effective execution (HWNE) signal that executes an instruction via the non-effective execution scheme at an instruction level of a processor based on hardware, or a software non-effective execution (SWNE) signal that executes a function via the non-effective execution scheme at a function level including instructions based on software.

18. The method of claim 16, further comprising:

storing, in a memory, the EPI corresponding to a thread for each thread; and

copying a current value of the EPC to be the EPI in the memory when the thread is in a running state.

19. The method of claim 16, further comprising:

copying a value of the EPC to be the EPI in a memory at a point in time at which a first thread context-switches to a second thread; and

loading the EPI copied in the memory to the EPC in response to the second thread context-switching back to the first thread.

20. A method for thread progress tracking, the method comprising:

selecting a thread prepared according to an instruction to be executed on a scheduler;

setting an effective progress index (EPI) stored in the thread to an initial value of an effective progress counter (EPC), and setting a kernel progress index (KPI) stored in the thread to an initial value of a kernel progress counter (KPC);

determining whether a flag value set to indicate that a non-effective function in use is set in a thread control block of the thread;

suspending the EPC by setting a software non-effective execution scheme (SWNE) signal, and operating the KPC by setting a kernel progress software (KPSW) signal when the flag value is set; and

correcting an increment of an EPC not used for effectively executing code of the thread, operating the suspended EPC by clearing the SWNE signal, and suspending the KPC by clearing the KPSW signal when the flag value fails to be set.

21. A method for thread progress tracking, the method comprising:

suspending an effective progress counter (EPC) by setting a software non-effective execution scheme (SWNE) signal, and operating a kernel progress counter (KPC) by setting a kernel progress software (KPSW) signal in response to a schedule event occurring in a thread in a running state;

storing a value of the suspended EPC to be a value of an effective progress index (EPI) in a memory in response to a context switch event occurring in a state in which the EPC is suspended; and

correcting an increment of an EPC not used for effectively executing code of the thread, operating the suspended EPC by clearing the SWNE signal, and suspending the KPC by clearing the KPSW signal in response to the schedule event being terminated in a state in which the EPC is suspended.