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Data processor device having a debug control module which selectively modifies trace messages

  • US 9,223,678 B2
  • Filed: 07/31/2013
  • Issued: 12/29/2015
  • Est. Priority Date: 07/31/2013
  • Status: Active Grant
First Claim
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1. A data processing system comprising:

  • an interconnect;

    a central processing unit coupled to the interconnect;

    a memory coupled to the interconnect, the memory is accessed by the central processing unit via the interconnect;

    a debug circuit coupled to the interconnect, the debug circuit including;

    a trace module;

    a watchpoint module;

    a trace message buffer;

    a debug control module configured todetect a specified system event,examine a plurality of messages in the trace message buffer for at least one characteristic, andselectively remove at least a portion of one or more of the plurality of messages that have the at least one characteristic; and

    a control register having a parameter that indicates whether the ability to remove the at least a portion of one or more of the plurality of messages is enabled.

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