Verifying data of a dispersed storage network

• US 9,223,723 B2
• Filed: 09/16/2013
• Issued: 12/29/2015
• Est. Priority Date: 10/30/2012
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Cleversafe Incorporated (International Business Machines Corporation)
• Inventors: Peake, Andrew George, Resch, Jason K., Volvovski, Ilya
• Primary Examiner(s): Butler, Sarai
• Application Number:
  US14/027,694
• Publication Number:
  US 20140122925A1
• Time in Patent Office: 834 Days
• Field of Search: 714/42
• US Class Current: 1/1
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: H03M 13/616 Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations

Abstract

A method begins by a dispersed storage (DS) processing module of a storage unit receiving, over time, access requests regarding reading or writing of various data blocks. The method continues with the DS processing module establishing an internal verification access rate for verifying data blocks stored in a memory device of the storage unit based on a rate of the access requests and a maximum access rate of the memory device. The method continues with the DS processing module generating internal verification requests in accordance with the internal verification access rate, coordinating the internal verification requests and the access requests for accessing the memory device, and accessing the memory device based on the internal verification requests to verify the data blocks.

Claims

1. A method for execution by one or more processing modules of a storage unit of a dispersed storage network (DSN), the method comprises:

receiving, over time, a plurality of access requests regarding reading or writing of various data blocks, wherein the storage unit includes a plurality of memory devices and is assigned a range of logical DSN addresses, wherein each memory device of the plurality of memory devices is assigned a sub-range of logical DSN addresses of the range of logical DSN addresses, and wherein each of the plurality of access requests includes a logical DSN address for at least one of the various data blocks; and

for each of the plurality of memory devices;

establishing an internal verification access rate for verifying at least some data blocks of the various data blocks stored therein based on a rate of a corresponding portion of the plurality of access requests and a maximum access rate of the memory device;

generating internal verification requests in accordance with the internal verification access rate;

coordinating the internal verification requests and the corresponding portion of the plurality of access requests for accessing the memory device; and

accessing the memory device based on the internal verification requests to verify the at least some of the data blocks stored therein.

2. The method of claim 1, wherein the establishing the internal verification access rate further comprises:

utilizing a desired rate of data block verification to establish the internal verification access rate, wherein the desired rate of data block verification specifies a desired frequency at which the data blocks stored in the storage unit are to be verified.

3. The method of claim 1, wherein the establishing the internal verification access rate further comprises:

utilizing a target access rate to establish the internal verification access rate, wherein the target access rate specifies a percentage of the maximum access rate.

4. The method of claim 1, wherein the establishing the internal verification access rate further comprises:

determining an offset rate from the rate of the corresponding portion of the plurality of access requests, wherein a sum of the offset rate and the rate of the corresponding portion of the plurality of access requests is at most equal to the maximum access rate; and

utilizing the offset rate as the internal verification access rate.

5. The method of claim 1 further comprises:

the various data blocks corresponding to a plurality of encoded data slices, wherein a first encoded data slice of the plurality of encoded data slices corresponds to a first data segment and a second encoded data slice of the plurality of encoded data slices corresponds to a second data segment, wherein the first data segment is dispersed storage error encoded into a first set of encoded data slices and the second data segment is dispersed storage error encoded into a second set of encoded data slices, wherein the first set of encoded data slices includes the first encoded data slice and the second set of encoded data slices includes the second encoded data slice, wherein other encoded data slices of the first and second sets of encoded data slices are stored in other storage units, and wherein a threshold number of encoded data slices of the first set of encoded data slices is needed to reproduce the first data segment;

for the memory device storing the first encoded data slice, determining verification status of the other encoded data slices of the first set of encoded data slices; and

utilizing the verification status of the other encoded data slices of the first set of encoded data slices to establish the internal verification access rate for the memory device storing the first encoded data slice.

6. The method of claim 5 further comprises:

when the memory device storing the first encoded data slice is accessed to verify the first encoded data slice, performing a verification on the first encoded data slice; and

when the first encoded data slice fails the verification, flagging the first encoded data slice for rebuilding.

7. The method of claim 5 further comprises:

interpreting the verification status of the other encoded data slices of the first set of encoded data slices to determine whether at least a portion of the first data segment is in a rebuilding state; and

when the at least the portion of the first data segment is in the rebuilding state, establishing the internal verification access rate to exclude the first encoded data slice from verification for one or more memory access time intervals.

8. The method of claim 1, wherein the coordinating the internal verification requests and the corresponding portion of the plurality of access requests for accessing the memory device further comprises:

identifying a read request for a particular data block within the corresponding portion of the plurality of access requests for accessing the memory device;

determining whether the particular data block is one of the at least some of the data blocks to be verified; and

when the particular data block is the one of the at least some of the data blocks to be verified, reading the particular data block once to fulfill the read request and a corresponding one of the internal verification requests.

9. The method of claim 1 further comprises:

determining the rate of the corresponding portion of the plurality of access requests based on frequency of receiving the corresponding portion of the plurality of access requests and size of data blocks addressed in the corresponding portion of the plurality of access requests.

10. A dispersed storage (DS) module of a storage unit of a dispersed storage network (DSN), the DS module comprises:

an external access module, when operable within the storage unit, causes the storage unit to;

receive, over time, a plurality of access requests regarding reading or writing of various data blocks, wherein the storage unit includes a plurality of memory devices and is assigned a range of logical DSN addresses, wherein each memory device of the plurality of memory devices is assigned a sub-range of logical DSN addresses of the range of logical DSN addresses, and wherein each of the plurality of access requests includes a logical DSN address for at least one of the various data blocks;

a verification rate module, when operable within the storage unit, causes the storage unit to;

for each of the plurality of memory devices, establish an internal verification access rate for verifying at least some data blocks of the various data blocks stored therein based on a rate of a corresponding portion of the plurality of access requests and a maximum access rate of the memory device;

an internal access module, when operable within the storage unit, causes the storage unit to;

generate internal verification requests in accordance with the internal verification access rate; and

coordinate the internal verification requests and the corresponding portion of the plurality of access requests for accessing the memory device; and

an integrity verification module, when operable within the storage unit, causes the storage unit to;

access the memory device based on the internal verification requests to verify the at least some of the data blocks stored therein.

11. The DS module of claim 10, wherein the verification rate module further functions to establish the internal verification access rate by:

utilizing a desired rate of data block verification to establish the internal verification access rate, wherein the desired rate of data block verification specifies a desired frequency at which the data blocks stored in the storage unit are to be verified.

12. The DS module of claim 10, wherein the verification rate module further functions to establish the internal verification access rate by:

utilizing a target access rate to establish the internal verification access rate, wherein the target access rate specifies a percentage of the maximum access rate.

13. The DS module of claim 10, wherein the verification rate module further functions to establish the internal verification access rate by:

determining an offset rate from the rate of the corresponding portion of the plurality of access requests, wherein a sum of the offset rate and the rate of the corresponding portion of the plurality of access requests is at most equal to the maximum access rate; and

utilizing the offset rate as the internal verification access rate.

14. The DS module of claim 10 further comprises:

the various data blocks corresponding to a plurality of encoded data slices, wherein a first encoded data slice of the plurality of encoded data slices corresponds to a first data segment and a second encoded data slice of the plurality of encoded data slices corresponds to a second data segment, wherein the first data segment is dispersed storage error encoded into a first set of encoded data slices and the second data segment is dispersed storage error encoded into a second set of encoded data slices, wherein the first set of encoded data slices includes the first encoded data slice and the second set of encoded data slices includes the second encoded data slice, wherein other encoded data slices of the first and second sets of encoded data slices are stored in other storage units, and wherein a threshold number of encoded data slices of the first set of encoded data slices is needed to reproduce the first data segment; and

the verification rate module, when operable within the storage unit, further causes the storage unit to;

for the memory device storing the first encoded data slice, determine verification status of the other encoded data slices of the first set of encoded data slices; and

utilize the verification status of the other encoded data slices of the first set of encoded data slices to establish the internal verification access rate for the memory device storing the first encoded data slice.

15. The DS module of claim 14 further comprises:

the integrity verification module, when operable within the storage unit, further causes the storage unit to;

when the memory device storing the first encoded data slice is accessed to verify the first encoded data slice, perform a verification on the first encoded data slice; and

when the first encoded data slice fails the verification, flag the first encoded data slice for rebuilding.

16. The DS module of claim 14 further comprises:

the verification rate module, when operable within the storage unit, further causes the storage unit to;

interpret the verification status of the other encoded data slices of the first set of encoded data slices to determine whether at least a portion of the first data segment is in a rebuilding state; and

when the at least the portion of the first data segment is in the rebuilding state, establish the internal verification access rate to exclude the first encoded data slice from verification for one or more memory access time intervals.

17. The DS module of claim 10, wherein the internal access module further functions to coordinate the internal verification requests and the corresponding portion of the plurality of access requests for accessing the memory device by:

identifying a read request for a particular data block within the corresponding portion of the plurality of access requests for accessing the memory device;

determining whether the particular data block is one of the at least some of the data blocks to be verified; and

when the particular data block is the one of the at least some of the data blocks to be verified, reading the particular data block once to fulfill the read request and a corresponding one of the internal verification requests.

18. The DS module of claim 10 further comprises:

the external access module, when operable within the storage unit, further causes the storage unit to;

determine the rate of the corresponding portion of the plurality of access requests based on frequency of receiving the corresponding portion of the plurality of access requests and size of data blocks addressed in the corresponding portion of the plurality of access requests.