Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness

• US 9,223,925 B2
• Filed: 04/07/2014
• Issued: 12/29/2015
• Est. Priority Date: 07/24/2010
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Krishnan, Prakash, McSherry, Michael, White, David, Fischer, Ed, Yanagida, Bruce, Dennison, Keith
• Primary Examiner(s): Dinh, Paul
• Application Number:
  US14/247,236
• Publication Number:
  US 20140237440A1
• Time in Patent Office: 631 Days
• Field of Search: 716103-107, 716110-111, 716/115, 716/123, 716/100
• US Class Current: 1/1
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.

Claims

1. A computer implemented method for implementing an electronic circuit design of an electronic circuit with simulation awareness, comprising:

identifying physical data that includes data for a net or one or more shapes that are part of the net in a partial layout of the electronic circuit design, wherein the partial layout is incomplete to pass a layout versus schematic check;

identifying or generating first simulation results of simulating a schematic design of the electronic circuit design with an electrical parasitic associated with the physical data;

identifying modified physical data of the physical data in the electronic circuit design;

simulating, with an aid of a parasitic aware simulation mechanism including or coupled with at least one processor of a computing system, the electronic circuit design by performing a second simulation on at least a portion of the schematic design with a new electrical parasitic or an updated electrical parasitic of the electrical parasitic to generate second simulation results;

modifying at least a part of the partial layout based in part or in whole upon the second simulation results, wherein the electronic circuit design including the at least the part of the partial layout that has been modified is used to manufacture the electronic circuit.

2. The computer implemented method of claim 1, further comprising:

modifying the schematic design or the layout of the electronic circuit design at least by comparing the first simulation results with the second simulation results.

3. The computer implemented method of claim 1, further comprising:

identifying or creating the schematic design for the electronic circuit;

identifying or generating a netlist from the schematic design; and

mapping the electrical parasitic to the schematic design, wherein a first simulation that generates the first simulation results is performed by using the electrical parasitic that is mapped to the schematic design.

4. The computer implemented method of claim 1, further comprising at least one of:

comparing the second simulation results with the first simulation results;

generating a netlist directly from the partial layout of the electronic circuit without identifying or creating the schematic design of the electronic circuit;

comparing the first simulation results before the act of identifying the physical data with the second simulation results after the act of identifying the physical data;

improving a component parameter based at least in part upon a result of comparing the first simulation results with the second simulation results; and

reducing the new electrical parasitic or the updated electrical parasitic to an approximate form or an alternative form.

5. The computer implemented method of claim 1, further comprising at least one of:

performing a sampling process on one or more transient simulation waveforms, and providing the one or more transient simulation waveforms that are sampled to a physical electronic circuit design tool; and

assembling the electrical characteristic that is associated with the electrical parasitic, the updated electrical parasitic, or the new electrical parasitic, wherein simulations are performed at a first level using at least the electrical characteristic that is assembled.

6. The computer implemented method of claim 1, further comprising at least one of:

synchronizing a first data for the schematic design and a second data for the partial layout of the electronic circuit;

flattening a schematic hierarchy, and stitching the electrical parasitic to the schematic hierarchy that is flattened; and

identifying the schematic hierarchy, performing a mapping or a binder process between the schematic design and the partial layout of the electronic circuit, and stitching the electrical parasitic to the schematic hierarchy that is hierarchical.

7. A system for implementing an electronic circuit design of an electronic circuit with simulation awareness, comprising:

at least one processor that executes a sequence of instructions;

a non-transitory computer accessible medium storing thereupon program code which, when executed by the at least one processor, causes the at least one processor to;

identify physical data that includes data for a net or one or more shapes that are part of the net in a partial layout of the electronic circuit design, wherein the partial layout is incomplete to pass a layout versus schematic check;

identify or generate first simulation results of simulating a schematic design of the electronic circuit design with an electrical parasitic associated with the physical data;

identify modified physical data of the physical data in the electronic circuit design;

simulate, with an aid of a parasitic aware simulation mechanism including or coupled with the at least one processor of a computing system, the electronic circuit design by performing a second simulation on at least a portion of the schematic design with new or updated electrical parasitic to generate second simulation results;

modify at least a part of the electronic circuit design based in part or in whole upon the second simulation results, wherein the electronic circuit design including the at least the part of the partial layout that has been modified is used to manufacture the electronic circuit.

8. The system of claim 7, in which the at least one processor further executes the program code to:

modify the schematic or the partial layout of the electronic circuit design at least by comparing the second simulation results with the first simulation results.

9. The system of claim 7, in which the at least one processor further executes the program code to:

identify or create the schematic design for the electronic circuit;

identify or generate a netlist from the schematic design; and

map the electrical parasitic to the schematic design, wherein a first simulation generating the first simulation results is performed by using the electrical parasitic that is mapped to the schematic design.

10. The system of claim 7, in which the processor further executes the program code to:

compare the second simulation results with the first simulation results;

generate a netlist directly from partial layout without identifying or creating the schematic design;

compare the first simulation results before identifying the modified physical data and the second simulation results after the act of identifying the modified physical data;

improve a component parameter based at least in part upon a result of comparing the first simulation results and the second simulation results;

or

reduce the electrical parasitic to an approximate form or an alternative form.

11. The system of claim 7, in which the processor further executes the program code to:

perform a sampling process on one or more transient simulation waveforms, and providing the one or more transient simulation waveforms that are sampled to a physical electronic circuit design tool;

or

assemble the electrical characteristic that is associated with the electrical parasitic, the updated electrical parasitic, or the new electrical parasitic, wherein simulations are performed at a first level using at least the electrical characteristic that is assembled.

12. The system of claim 7, in which the processor further executes the program code to:

synchronize a first data for the schematic design and a second data for the partial layout of the electronic circuit;

flatten a schematic hierarchy, and stitching the electrical parasitic to the schematic hierarchy that is flattened;

or

identify the schematic hierarchy, performing a mapping or a binder process between the schematic design and the partial layout, and stitching the electrical parasitic to the schematic hierarchy that is hierarchical.

13. An article of manufacture comprising a non-transitory computer readable medium having stored thereupon a sequence of instructions which, when executed by at least one processor, causes the processor to execute a set of acts for implementing an electronic circuit design of an electronic circuit with simulation awareness, the set of acts comprising:

identifying physical data that includes data for a net or one or more shapes that are part of the net in a partial layout of the electronic circuit design, wherein the partial layout is incomplete to pass a layout versus schematic check;

identify or generate first simulation results of simulating a schematic design of the electronic circuit design with an electrical parasitic associated with the physical data;

identifying modified physical design data of the physical data in the electronic circuit design;

simulating, with an aid of a parasitic aware simulation mechanism including or coupled with at least one processor of a computing system, the electronic circuit design by performing a second simulation on at least a portion of the schematic design with new or updated electrical parasitic to generate second simulation results;

modifying at least a part of the electronic circuit design based in part or in whole upon the second simulation results, wherein the electronic circuit design including the at least the part of the partial layout that has been modified is used to manufacture the electronic circuit.

14. The article of manufacture of claim 13, the set of acts further comprising:

modifying the schematic or the partial layout at least by comparing the second simulation results with the first simulation results.

15. The article of manufacture of claim 13, the set of acts further comprising:

identifying or creating the schematic design for the electronic circuit;

identifying or generating a netlist from the schematic design; and

mapping the electrical parasitic to the schematic design, wherein a first simulation generating the first simulation results is performed by using the electrical parasitic that is mapped to the schematic design.

16. The article of manufacture of claim 13, the set of acts further comprising at least one of:

comparing the second simulation results with the first simulation results;

generating a netlist directly from the partial layout without identifying or creating the schematic design of the electronic circuit;

comparing the first simulation results of the simulation before the act of identifying-the physical data and the second results after the act of identifying the physical data;

improving a component parameter based at least in part upon a result of comparing the first results and the second simulation results; and

reducing the electrical parasitic to an approximate form or an alternative form.

17. The article of manufacture of claim 13, the set of acts further comprising at least one of:

performing a sampling process on one or more transient simulation waveforms, and providing the one or more transient simulation waveforms that are sampled to a physical electronic circuit design tool; and

assembling the electrical characteristic that is associated with the electrical parasitic, the updated electrical parasitic, or the new parasitic, wherein the simulation is performed at a first level using at least the electrical characteristic that is assembled.

18. The article of manufacture of claim 13, the set of acts further comprising at least one of:

synchronizing a first data for the schematic design and a second data for the partial layout;

flattening a schematic hierarchy, and stitching the electrical parasitic to the schematic hierarchy that is flattened; and

identifying the schematic hierarchy, performing a mapping or a binder process between the schematic design and the partial layout, and stitching the electrical parasitic to the schematic hierarchy that is hierarchical.

19. A computer implemented method for implementing an electronic circuit design of an electronic circuit with simulation awareness, comprising:

identifying first physical data for a first net or one or more first shapes that are part of the first net in a partial layout of the electronic circuit design, wherein the partial layout is incomplete to pass a layout versus schematic check;

identifying or generating first simulation results of performing a first simulation on a schematic design of the electronic circuit design with a first electrical parasitic associated with the first physical data;

identifying second physical data for a second net or one or more second shapes that are part of the second net in the electronic circuit design;

simulating, with an aid of a parasitic aware simulation mechanism including or coupled with at least one processor of a computing system, the electronic circuit design by performing a second simulation on at least a portion of the schematic design with new electrical parasitic or an updated first electrical parasitic of the first electrical parasitic to generate second simulation results;

modifying at least a part of the electronic circuit design based in part or in whole upon the second simulation results, wherein the electronic circuit design including the at least the part of the partial layout that has been modified is used to manufacture the electronic circuit.

20. The computer implemented method of claim 19, further comprising:

identifying or creating the schematic design for the electronic circuit;

identifying or generating a netlist from the schematic design;

mapping one or more electrical parasitics to the schematic design, wherein the first simulation is performed by using the one or more electrical parasitics that are mapped to the schematic design; and

modifying the schematic design or the partial layout at least by comparing the first simulation results with the second simulation results.

21. The computer implemented method of claim 19, further comprising at least one of:

generating a netlist directly from the partial layout without identifying or creating the schematic design;

comparing the first simulation results with the second simulation results;

improving a component parameter based at least in part upon a part of the first simulation results or the second simulation results; and

reducing the first electrical parasitic or the second electrical parasitic to an approximate form or an alternative form.

22. A system for implementing an electronic circuit design of an electronic circuit with simulation awareness, the system comprising:

at least one processor that executes a sequence of instructions;

a non-transitory computer accessible medium storing thereupon program code which, when executed by the at least one processor, causes the at least one processor to;

identify first physical data for a first net or one or more first shapes that are part of the first net in a partial layout of the electronic circuit design, wherein the partial layout is incomplete to pass a layout versus schematic check;

identify or generate first simulation results of performing a first simulation on a schematic design of the electronic circuit design with a first electrical parasitic associated with the first physical data;

identify second physical data for a second net or one or more second shapes that are part of the second net;

simulate, with an aid of a parasitic aware simulation mechanism including or coupled with at least one processor of a computing system, the electronic circuit design by performing a second simulation on at least a portion of the schematic design with new electrical parasitic or an updated first electrical parasitic of the first electrical parasitic to generate second simulation results;

modify at least a part of the electronic circuit design based in part or in whole upon the second simulation results, wherein the electronic circuit design including the at least the part of the partial layout that has been modified is used to manufacture the electronic circuit.

23. The system of claim 22, wherein the at least one processor further executes the sequence of instructions to:

identify or create the schematic design for the electronic circuit;

identify or generate a netlist from the schematic design;

map one or more electrical parasitics to the schematic design, wherein the first simulation is performed by using the one or more electrical parasitics that are mapped to the schematic design; and

modify the schematic design or the partial layout at least by comparing the first simulation results with the second simulation results.

24. The system of claim 22, wherein the at least one processor further executes the sequence of instructions to:

generate a netlist directly from the partial layout without identifying or creating the schematic design;

compare the first simulation results with the second simulation results;

improve a component parameter based at least in part upon a part of the first simulation results or the second simulation results;

or

reduce the first electrical parasitic or the second electrical parasitic to an approximate form or an alternative form.

25. An article of manufacture comprising a non-transitory computer readable storage medium having stored thereupon a sequence of instructions which, when executed by at least one computer processor, cause the at least one processor to execute a set of acts for implementing an electronic circuit design of an electronic circuit with simulation awareness, the set of acts comprising:

identifying first physical data for a first net or one or more first shapes that are part of the first net in a partial layout of the electronic circuit design, wherein the partial layout is incomplete to pass a layout versus schematic check;

identify or generate first simulation results of performing a first simulation on a schematic design of the electronic circuit design with a first electrical parasitic associated with the first physical data;

identifying second physical data for a second net or one or more second shapes that are part of the second net in the electronic circuit design;

simulating, with an aid of a parasitic aware simulation mechanism including or coupled with at least one processor of a computing system, the electronic circuit design by performing a second simulation on at least a portion of the schematic design with new electrical parasitic or an updated first electrical parasitic of the first electrical parasitic to generate second simulation results;

modifying at least a part of the electronic circuit design based in part or in whole upon the second simulation results, wherein the electronic circuit design including the at least the part of the partial layout that has been modified is used to manufacture the electronic circuit.

26. The article of manufacture of claim 25, the set of acts further comprising:

identifying or creating the schematic design for the electronic circuit;

identifying or generating a netlist from the schematic design;

mapping one or more electrical parasitics to the schematic design, wherein the first simulation is performed by using the one or more electrical parasitics that are mapped to the schematic design; and

modifying the schematic design or the partial layout at least by comparing the first simulation results with the second simulation results.

27. The article of manufacture of claim 25, the set of acts further comprising at least one of:

generating a netlist directly from the partial layout without identifying or creating the schematic design of the electronic circuit;

comparing the first simulation results with the second simulation results;

improving a component parameter based at least in part upon a part of the first simulation results or the second simulation results; and

reducing the first electrical parasitic or the second electrical parasitic to an approximate form or an alternative form.