Voltage generating circuit

• US 9,224,434 B2
• Filed: 03/08/2013
• Issued: 12/29/2015
• Est. Priority Date: 08/30/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hong, Hyun-Sung
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): DINH, MINH D
• Application Number:
  US13/791,129
• Publication Number:
  US 20140063981A1
• Time in Patent Office: 1,026 Days
• Field of Search: 365/189.09, 365/203, 365/205
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A circuit includes a first transistor of a first type, a second transistor of a second type, a sense amplifier, a first data line, and a second data line. The second type is different from the first type. The first data line is coupled with a first terminal of the sense amplifier. The second data line is coupled with a second terminal of the sense amplifier. A first terminal of the first transistor is configured to receive a supply voltage. A second terminal of the first transistor, a third terminal of the first transistor, a second terminal of the second transistor, a third terminal of the second transistor are coupled together and are configured to carry a voltage. A first terminal of the second transistor is configured to receive a reference supply voltage. The first and second data lines are configured to receive a voltage value of the voltage.

Claims

1. A circuit comprising:

a sub circuit configured to generate a first voltage value, a second voltage value, and a third voltage value;

a switching circuit configured to selectively transfer the first voltage value, the second voltage value, or the third voltage value to an output voltage based on control signals; and

a switching control circuit configured to receive a first reference voltage value, a second reference voltage value, and the second voltage value, and, generate the control signals of the switching circuit based on

a first relationship between the first reference voltage value and the second voltage value, and

a second relationship between the second reference voltage value and the second voltage value.

2. The circuit of claim 1, wherein

the switching circuit includes a first switch, a second switch, and a third switch;

and

the switching control circuit is configured to generate a first control signal, a second control signal, and a third control signal of the control signals;

the first switch is configured to be controlled by the first control signal;

the second switch is configured to be controlled by the second control signal; and

the third switch is configured to be controlled by the third control signal.

3. The circuit of claim 1, further comprising:

a first voltage generating circuit configured to provide the first reference voltage value having a first self-adjustable voltage value; and

a second voltage generating circuit configured to provide the second reference voltage value having a second self-adjustable voltage value.

4. The circuit of claim 1, further comprising a sense amplifier, a first data line and a second data line, wherein

the first data line is coupled with a first terminal of the sense amplifier;

the second data line is coupled with a second terminal of the sense amplifier; and

the first data line and the second data line are configured to selectively receive the first voltage value, the second voltage value, or the third voltage value.

5. The circuit of claim 4, wherein

the sense amplifier includes a first inverter and a second inverter that form a cross latch;

the first inverter has a first voltage transfer curve;

the second inverter has a second voltage transfer curve;

the first voltage transfer curve and the second voltage transfer curve include a cross point; and

the second voltage value is selected based on the cross point.

6. The circuit of claim 5, wherein

the cross point and an origin of a first coordinate and a second coordinate of the first and second voltage transfer curves form a line;

and

the second voltage value is on the line.

7. The circuit of claim 1, further comprising

a first voltage generating circuit configured to provide the first reference voltage value having first different voltage values in different process corners;

and

a second voltage generating circuit configured to provide the second reference voltage value having second different voltage values in different process corners.

8. The circuit of claim 1, further comprising:

a first voltage generating circuit that includes a first inverter having an input coupled with an output and configured to provide the first reference voltage value; and

a second voltage generating circuit that includes a second inverter having an input coupled with an output and configured to provide the second reference voltage value different from the first reference voltage value.

9. The circuit of claim 1, further comprising:

a first voltage generating circuit that includes a first inverter formed by a first transistor of a first type coupled in series with a second transistor of a second type different from the first type, wherein the first transistor has a driving capability stronger than a driving capability of the second transistor; and

a second voltage generating circuit that includes a second inverter formed by a third transistor of the first type coupled in series with a fourth transistor of the second type, wherein the fourth transistor has a driving capability stronger than a driving capability of the third transistor.

10. The circuit of claim 1, further comprising:

a first voltage generating circuit that includes a first transistor of a first type and a second transistor of a second type different from the first type,

wherein

a first terminal of the first transistor is configured to receive a supply voltage;

a second terminal of the first transistor, a third terminal of the first transistor, a second terminal of the second transistor, and a third terminal of the second transistor are coupled together and are configured to provide the first reference voltage value; and

a first terminal of the second transistor is configured to receive a reference supply voltage;

a second voltage generating circuit that includes a third transistor of the first type and a fourth transistor of the second type,

wherein

a first terminal of the third transistor is configured to receive the supply voltage;

a second terminal of the third transistor, a third terminal of the third transistor, a second terminal of the fourth transistor, a third terminal of the fourth transistor are coupled together and are configured to provide the second reference voltage value; and

a first terminal of the fourth transistor is configured to receive the reference supply voltage.

11. The circuit of claim 1, wherein

the switching control circuit includes a first comparator, a second comparator, and a switching logic;

the first comparator is configured to provide a first comparator output based on the first reference voltage value and the second voltage value;

the second comparator is configured to provide a second comparator output based on the second reference voltage value and the second voltage value; and

the switching logic is configured to generate the control signals of the switching circuit based on the first comparator output and the second comparator output.

12. The circuit of claim 1, wherein

in a first process corner, the second voltage value is lower than both the first reference voltage value and the second reference voltage value;

in a second process corner, the second voltage value is lower than the first reference voltage value, and is higher than second reference voltage value; and

in a third process corner, the second voltage value is higher than both the first reference voltage value and the second reference voltage value.

13. The circuit of claim 12, wherein

in the first process corner, a driving capability of an N-type transistor in the circuit is lower than a driving capability of a P-type transistor in the circuit;

in the second process corner, the driving capability of the N-type transistor is about the same as the driving capability of the P-type transistor; and

in the third process corner, the driving capability of the N-type transistor is higher than the driving capability of the P-type transistor.

14. The circuit of claim 1, wherein

the sub circuit includes a voltage divider configured to generate the first voltage value, the second voltage value, and the third voltage value.

15. A circuit comprising:

a sub circuit configured to generate a plurality of voltage signals having different voltage values;

a switching circuit configured to selectively output one of the plurality of voltage signals as an output voltage of the switching circuit based on a set of control signals; and

a switching control circuit configured to generate the set of control signals based on a first comparison result and a second comparison result, the first comparison result corresponding to comparing a voltage level of a first reference voltage and a voltage level of a predetermined one of the plurality of voltage signals, and the second comparison result corresponding to comparing a voltage level of a second reference voltage and the voltage level of the predetermined one of the plurality of voltage signals.

16. The circuit of claim 15, further comprising:

a first voltage generating circuit configured to generate the first reference voltage; and

a second voltage generating circuit configured to generate the second reference voltage,

wherein the first voltage generating circuit, the second voltage generating circuit, and the sub circuit are configured such that

the voltage level of the predetermined one of the plurality of voltage signals is between the voltage levels of the first reference voltage and the second reference voltage when the circuit is in a typical typical (TT) process corner;

the voltage level of the predetermined one of the plurality of voltage signals is less than the voltage levels of the first reference voltage and the second reference voltage when the circuit is in a fast slow (FS) process corner; and

the voltage level of the predetermined one of the plurality of voltage signals is greater than the voltage levels of the first reference voltage and the second reference voltage when the circuit is in a slow fast (SF) process corner.

17. The circuit of claim 15, further comprising:

a first voltage generating circuit configured to generate the first reference voltage, the first voltage generating circuit comprising;

a first P-type transistor having a gate and a drain; and

a first N-type transistor having a gate and a drain,

the gate and the drain of the first P-type transistor and the gate and the drain of the first N-type transistor electrically coupled together and configured to carry the first reference voltage; and

a driving capability of the first P-type transistor being greater than a driving capability of the first N-type transistor; and

a second voltage generating circuit configured to generate the second reference voltage, the second voltage generating circuit comprising;

a second P-type transistor having a gate and a drain; and

a second N-type transistor having a gate and a drain,

the gate and the drain of the second P-type transistor and the gate and the drain of the second N-type transistor electrically coupled together and configured to carry the second reference voltage; and

a driving capability of the second N-type transistor being greater than a driving capability of the second P-type transistor.

18. A circuit comprising:

a voltage divider configured to output a first voltage having a first voltage level, a second voltage having a second voltage level, and a third voltage having a third voltage level, the first voltage level being greater than the second voltage level, and the second voltage level being greater than the third voltage level;

a first voltage generating circuit configured to generate a first reference voltage, the first reference voltage having a first reference voltage level, the first reference voltage level being greater than the second voltage level when the circuit is in a typical typical (TT) process corner, and less than the second voltage level when the circuit is in a fast slow (FS) process corner; and

a second voltage generating circuit configured to generate a second reference voltage, the second reference voltage having a second reference voltage level, the second reference voltage level being less than the second voltage level when the circuit is in the TT process corner, and greater than the second voltage level when the circuit is in a slow fast (SF) process corner;

a switching control circuit configured to generate a set of control signals based on comparing the second voltage level, the first reference voltage level, and the second reference voltage level; and

a switching circuit configured to selectively output one of the first voltage, the second voltage, or the third voltage as an output voltage of the switching circuit based on the set of control signals.

19. The circuit of claim 18, wherein

the first voltage generating circuit comprises:

a first P-type transistor having a gate and a drain; and

a first N-type transistor having a gate and a drain,

the gate and the drain of the first P-type transistor and the gate and the drain of the first N-type transistor electrically coupled together and configured to carry the first reference voltage; and

a driving capability of the first P-type transistor being greater than a driving capability of the first N-type transistor; and

the second voltage generating circuit comprises;

a second P-type transistor having a gate and a drain; and

a second N-type transistor having a gate and a drain,

the gate and the drain of the second P-type transistor and the gate and the drain of the second N-type transistor electrically coupled together and configured to carry the second reference voltage; and

a driving capability of the second N-type transistor being greater than a driving capability of the second P-type transistor.

20. The circuit of claim 18, wherein

the switching control circuit comprises a first comparator, a second comparator, and a switching logic;

the first comparator is configured to provide a first comparator output based on the second voltage level and the first reference voltage level;

the second comparator is configured to provide a second comparator output based on the second voltage level and the second reference voltage level; and

the switching logic is configured to generate the set of control signals based on the first comparator output and the second comparator output.