Memory circuit and related method

• US 9,224,464 B2
• Filed: 02/10/2014
• Issued: 12/29/2015
• Est. Priority Date: 02/10/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chou, Chung-Cheng, Lee, Po-Hao, Chen, Jonathan Tehan
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US14/176,820
• Publication Number:
  US 20150228333A1
• Time in Patent Office: 687 Days
• Field of Search: 365/148, 365/158, 365/205
• US Class Current: 1/1
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/005 Read using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A device includes a memory bit cell, a first current source, and a current comparator electrically connected to the memory bit cell and the first current source. A first transistor has a first terminal electrically connected to a first voltage supply node, a control terminal electrically connected to a controller, and a second terminal electrically connected to the memory bit cell and the current comparator. A sense amplifier is electrically connected to the current comparator and a reference current generator.

Claims

1. A device comprising:

a reference current source;

a current mirror electrically connected to the reference current source and a memory bit cell;

a charging device electrically connected to the current mirror and the memory bit cell, and a first voltage supply node;

a first common source amplifier electrically connected to the current mirror and the memory bit cell;

a second common source amplifier electrically connected to a second voltage supply node; and

a sense amplifier electrically connected to the first and second common source amplifiers.

2. The device of claim 1, wherein the sense amplifier comprises:

a first inverter;

a second inverter cross-coupled with the first inverter; and

a precharging circuit having a first terminal electrically connected to an output terminal of the first inverter, and a second terminal electrically connected to an output terminal of the second inverter.

3. The device of claim 2, wherein the precharging circuit comprises:

a first transistor having;

a first terminal electrically connected to the output terminal of the first inverter; and

a second terminal electrically connected to the output terminal of the second inverter;

a second transistor having;

a first terminal electrically connected to the first voltage supply node; and

a second terminal electrically connected to the output terminal of the first inverter;

a third transistor having;

a first terminal electrically connected to the first voltage supply node;

a second terminal electrically connected to the output terminal of the second inverter; and

a control terminal electrically connected to control terminals of the first and second transistors.

4. The device of claim 1, further comprising:

a clamping device electrically connected to the memory bit cell and the current mirror.

5. The device of claim 4, further comprising:

a select transistor electrically connected to the clamping device and the memory bit cell.

6. The device of claim 5, wherein:

the clamping device is an N-type transistor; and

the select transistor is an N-type transistor.

7. A device comprising:

a memory bit cell;

a first current source;

a current comparator electrically connected to the memory bit cell and the first current source;

a first transistor having;

a first terminal electrically connected to a first voltage supply node;

a control terminal electrically connected to a controller; and

a second terminal electrically connected to the memory bit cell and the current comparator; and

a sense amplifier electrically connected to the current comparator, and a reference current generator.

8. The device of claim 7, wherein the first current source has a reference current source and a current mirror.

9. The device of claim 7, wherein the current comparator is an N-type transistor having a control terminal electrically connected to the memory bit cell and the first current source.

10. The device of claim 7, wherein the sense amplifier comprises:

a first inverter;

a second inverter cross-coupled with the first inverter; and

a precharging circuit having a first terminal electrically connected to an output terminal of the first inverter, and a second terminal electrically connected to an output terminal of the second inverter.

11. The device of claim 7, wherein the memory bit cell is a resistive random access memory (RRAM) bit cell, a magnetoresistive random-access memory (MRAM) bit cell, a phase-change random-access memory (PCRAM) bit cell, or a conductive-bridging random-access memory (CBRAM) bit cell.

12. The device of claim 11, further comprising a clamping device electrically connected to the memory bit cell and the first current source.

13. The device of claim 7, wherein the first transistor is a P-type metal-oxide-semiconductor (PMOS) transistor.

14. A method comprising:

(a) charging a signal voltage node;

(b) charging output nodes of a sense amplifier;

wherein the output nodes are different than the signal voltage node;

(c)after charging output nodes, activating a memory bit cell electrically connected to the signal voltage node;

(d)after activating the memory bit cell, modifying a signal voltage at the signal voltage node based on a cell current of the memory bit cell and a reference current;

(e) establishing a voltage difference across the output nodes of the sense amplifier based on the signal voltage and a reference voltage;

(f) latching the voltage difference to generate a rail-to-rail voltage difference; and

(g) determining polarity of data stored by the memory bit cell based on the rail-to-rail voltage difference.

15. The method of claim 14, wherein (a) includes:

charging the signal voltage node by a first transistor.

16. The method of claim 15, wherein (d) includes:

turning off the first transistor;

charging the signal voltage node by the reference current; and

discharging the signal voltage node by the cell current.

17. The method of claim 14, wherein (b) includes:

charging the output nodes of the sense amplifier to a first voltage by a precharging circuit of the sense amplifier.

18. The method of claim 17, wherein (e) includes:

discharging one of the output nodes by a first current generated based on the signal voltage; and

discharging the other of the output nodes by a second current generated based on the reference voltage.

19. The method of claim 14, wherein (f) includes turning on a current source electrically connected to the sense amplifier.

20. The method of claim 14, wherein (d) includes:

generating a current by a current source; and

mirroring the current to generate the reference current.