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Method to improve fine Cu line reliability in an integrated circuit device

  • US 9,224,640 B2
  • Filed: 08/17/2012
  • Issued: 12/29/2015
  • Est. Priority Date: 08/17/2012
  • Status: Expired due to Fees
First Claim
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1. A semiconductor structure, comprising:

  • a plurality of layers comprising at least a first layer and a dielectric layer above said first layer;

    at least one copper interconnect layer within a recess in said dielectric layer such that top surfaces of said dielectric layer and said at least one copper interconnect layer are essentially co-planar, said copper interconnect layer providing an electrical conduit between at least one of;

    physically adjacent layers in said semiconductor structure, andan integrated circuit in said semiconductor structure and an electronic device; and

    a plurality of studs extending vertically through said first layer and further protruding into said at least one copper interconnect layer from a bottom of said at least one copper interconnect layer,each of said studs having lower opposing sidewalls adjacent to said first layer and upper opposing sidewalls adjacent to said at least one copper interconnect layer,adjacent studs being spaced apart by a distance less than or equal to a Blech length of said at least one copper interconnect layer,said Blech length comprising a length below which damage due to electromigration of metal atoms within said at least one copper interconnect layer does not occur, andsaid plurality of studs comprising copper atom diffusion barriers based on spacing between said plurality of studs.

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