Semiconductor integrated circuit device

• US 9,224,725 B2
• Filed: 02/20/2015
• Issued: 12/29/2015
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: Usami, Shiro
• Primary Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US14/628,175
• Publication Number:
  US 20150171068A1
• Time in Patent Office: 312 Days
• Field of Search: 257/355
• US Class Current: 1/1
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 27/0292 using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes

Abstract

Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

Claims

1. A semiconductor integrated circuit device, comprising an ESD (Electro Static Discharge) protection circuit, wherein:

the ESD protection circuit comprises;

a first wiring extending in a first direction and electrically connected to a first terminal;

a second wiring and a third wiring, extending in the first direction, electrically connected to a power supply terminal or a ground terminal, and disposed on both sides of the first wiring, respectively;

a first diffusion region connected to and formed under the first wiring, having a first conductivity type, and disposed between the second wiring and the third wiring;

a second diffusion region connected to and formed under the second wiring, having a second conductivity type, and disposed so as to be opposed to the first diffusion region; and

a third diffusion region connected to and formed under the third wiring, having the second conductivity type, and disposed so as to be opposed to the first diffusion region,

the second diffusion region, the first diffusion region, and the third diffusion region are disposed in this order in a second direction perpendicular to the first direction,

the first conductivity type is different from the second conductivity type,

a space between the second wiring and the first diffusion region in the second direction is larger than a space between the second diffusion region and the first diffusion region in the second direction, in a planar view, and

a space between the third wiring and the first diffusion region in the second direction is larger than a space between the third diffusion region and the first diffusion region in the second direction, in a planar view.

2. The semiconductor integrated circuit device according to claim 1, wherein each of the first, second, and third diffusion regions has a rectangular shape, a length of the rectangular shape in the first direction being greater than a length of the rectangular shape in the second direction.

3. The semiconductor integrated circuit device according to claim 1, wherein the second and third diffusion regions are partially connected to each other through a diffusion region.

4. The semiconductor integrated circuit device according to claim 1, wherein:

a space between the first wiring and the second diffusion region in the second direction is larger than a space between the first diffusion region and the second diffusion region in the second direction, in a planar view, and

a space between the first wiring and the third diffusion region in the second direction is larger than a space between the first diffusion region and the third diffusion region in the second direction, in a planar view.

5. The semiconductor integrated circuit device according to claim 1, wherein the second wiring and the third wiring are electrically connected to the power supply terminal.

6. The semiconductor integrated circuit device according to claim 5, wherein:

the first conductivity type is a P type, and the second conductivity type is an N type, and

the ESD protection circuit is a diode type having the first terminal as an anode and the power supply terminal as a cathode.

7. The semiconductor integrated circuit device according to claim 1, wherein the second wiring and the third wiring are connected to the ground terminal.

8. The semiconductor integrated circuit device according to claim 7, wherein:

the first conductivity type is an N type, and the second conductivity type is a P type, and

the ESD protection circuit is a diode type having the ground terminal as an anode and the first terminal as a cathode.

9. The semiconductor integrated circuit device according to claim 1, wherein:

the first diffusion region includes a first portion and a second portion,

the first portion and the second portion are separated from each other,

the second diffusion region, the first portion, the second portion and the third diffusion region are disposed in this order in the second direction,

a space between the second wiring and the first portion in the second direction is larger than

a space between the second diffusion region and the first portion in the second direction, in a planar view, and

a space between the third wiring and the second portion in the second direction is larger than a space between the third diffusion region and the second portion in the second direction, in a planar view.

10. The semiconductor integrated circuit device according to claim 9, wherein each of the first portion, the second portion, the second diffusion region and the third diffusion region has a rectangular shape, a length of the rectangular shape in the first direction being greater than a length of the rectangular shape in the second direction.

11. The semiconductor integrated circuit device according to claim 9, wherein a length of each of the first and second portions in the second direction is smaller than a length of each of the second and third diffusion regions in the second direction.

12. The semiconductor integrated circuit device according to claim 9, wherein the second and third diffusion regions are partially connected to each other through a diffusion region.

13. The semiconductor integrated circuit device according to claim 9, wherein the first portion and the second portion are partially connected.

14. The semiconductor integrated circuit device according to claim 3, wherein each of the first, second, and third diffusion regions has a rectangular shape, a length of the rectangular shape in the first direction being greater than a length of the rectangular shape in the second direction.

15. The semiconductor integrated circuit device according to claim 3, wherein:

a space between the first wiring and the second diffusion region in the second direction is larger than a space between the first diffusion region and the second diffusion region in the second direction, in a planar view, and

a space between the first wiring and the third diffusion region in the second direction is larger than a space between the first diffusion region and the third diffusion region in the second direction, in a planar view.

16. The semiconductor integrated circuit device according to claim 3, wherein the second wiring and third wiring are electrically connected to the power supply terminal.

17. The semiconductor integrated circuit device according to claim 16, wherein:

the first conductivity type is a P type, and the second conductivity type is an N type, and

the ESD protection circuit is a diode type having the first terminal as an anode and the power supply terminal as a cathode.

18. The semiconductor integrated circuit device according to claim 3, wherein the second and third diffusion regions are partially connected to each other through two diffusion regions so as to surround the first diffusion region.

19. The semiconductor integrated circuit device according to claim 1, wherein:

the first diffusion region is connected to the first wiring via first contacts,

the second diffusion region is connected the second wiring via second contacts, and

the third diffusion region is connected to the third wiring via third contacts.

20. The semiconductor integrated circuit device according to claim 19, wherein:

the second diffusion region has first and second edges extending in the first direction,

the second edge is located closer to the first diffusion region than the first edge, and

a space between the first edge and one of the second contacts, which is closest to the first edge, in the second direction is smaller than a space between the second edge and one of the second contacts, which is closest to the second edge in the second direction, in a planar view.

21. The semiconductor integrated circuit device according to claim 1, wherein:

the ESD protection circuit further comprises;

a fourth wiring extending in the first direction; and

a fourth diffusion region that is connected to and formed under the fourth wiring, having the first conductivity type, and disposed such that the second diffusion region, the first diffusion region, the third diffusion region and the fourth diffusion region are disposed in this order in the second direction, and

a space between the third wiring and the fourth diffusion region in the second direction is larger than a space between the third diffusion region and the fourth diffusion region in the second direction, in a planar view.

22. The semiconductor integrated circuit device according to claim 21, wherein:

the fourth diffusion region includes a third portion and a fourth portion, the third portion and the fourth portion are separated from each other,

the second diffusion region, the first diffusion region, the third diffusion region, the third portion and the fourth portion are disposed in this order in the second direction, and

a space between the third wiring and the third portion in the second direction is larger than a space between the third diffusion region and the third portion in the second direction, in a planar view.

23. The semiconductor integrated circuit device according to claim 22, wherein the third portion and the fourth portion are partially connected.

24. The semiconductor integrated circuit device according to claim 21, wherein:

the ESD protection circuit further comprises;

a fifth wiring extending in the first direction; and

a fifth diffusion region connected to and formed under the fifth wiring, having the second conductivity type, and disposed such that the second diffusion region, the first diffusion region, the third diffusion region, the fourth diffusion region and the fifth diffusion region are disposed in this order in the second direction, and

a space between the fifth wiring and the fourth diffusion region in the second direction is larger than a space between the fifth diffusion region and the fourth diffusion region in the second direction, in a planar view.

25. The semiconductor integrated circuit device according to claim 24, wherein the third and fifth diffusion regions are partially connected to each other through a diffusion region.