Method of forming a vertical device

• US 9,224,833 B2
• Filed: 02/13/2014
• Issued: 12/29/2015
• Est. Priority Date: 02/13/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, De-Fang, Tsai, Teng-Chun, Lin, Cheng-Tung, Wang, Li-Ting, Lee, Chun-Hung, Chang, Ming-Ching, Lin, Huan-Just
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US14/179,983
• Publication Number:
  US 20150228759A1
• Time in Patent Office: 684 Days
• Field of Search: 438/696
• US Class Current: 1/1
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes the following operations: providing a vertical structure over a substrate; forming a first dielectric layer over the vertical structure and the substrate; laterally etching a sidewall of the first dielectric layer; replacing a portion of the first dielectric layer over the vertical structure with a second dielectric layer; and etching a portion of the first dielectric layer to expose the lateral surface of the vertical structure.

Claims

1. A method of forming a vertical device, comprising:

providing a vertical structure over a substrate;

forming a first dielectric layer over the vertical structure and the substrate;

laterally etching a sidewall of the first dielectric layer;

replacing a portion of the first dielectric layer over the vertical structure with a second dielectric layer; and

etching a portion of the first dielectric layer to expose the lateral surface of the vertical structure.

2. The method of claim 1, wherein replacing the portion of the first dielectric layer over the vertical structure with the second dielectric layer further comprises:

forming a first film layer over the first dielectric layer;

performing chemical mechanical polishing on the first film layer and stopping on the first dielectric layer;

etching a portion of the first dielectric layer to expose a top surface of the vertical structure and to form a recess;

forming the second dielectric layer over the first film layer and in the recess;

performing chemical mechanical polishing on the second dielectric layer and stopping on the first film layer; and

etching the first film layer.

3. The method of claim 2, wherein forming the first film layer over the first dielectric layer comprises forming the first film layer with at least one of poly and an ashable amorphous carbon film.

4. The method of claim 2, wherein forming the second dielectric layer over the first film layer and in the recess further comprises forming the second dielectric layer with at least one of oxide, SiN, SiON, SiC, SiCN and SiOCN.

5. The method of claim 1, wherein laterally etching the sidewall of the first dielectric layer further comprises:

forming a polymer layer over a portion of the first dielectric layer above a top of the vertical structure by using a polymer gas; and

laterally etching the sidewall of the first dielectric layer by using a plasma etching process with a lateral power.

6. The method of claim 1, further comprising:

forming a third dielectric layer over the substrate.

7. The method of claim 1, wherein forming the first dielectric layer over the vertical structure and the substrate further comprises forming the first dielectric layer with at least one of oxide, SiN, SiON, SiC, SiCN and SiOCN.

8. The method of claim 1, wherein forming the first dielectric layer over the vertical structure and the substrate further comprises forming the first dielectric layer having a thickness of about 5-40 nanometers.

9. The method of claim 1, wherein providing the vertical structure over the substrate further comprises providing the vertical structure having a source layer and a channel layer.

10. The method of claim 1, wherein providing the vertical structure over the substrate further comprises providing the vertical structure having a source layer, a drain layer and a channel layer.

11. A method of forming a vertical device, comprising:

providing a vertical structure over a substrate;

forming a first dielectric layer over the vertical structure and the substrate;

forming a polymer layer over a portion of the first dielectric layer above a top of the vertical structure;

laterally etching a sidewall of the first dielectric layer;

replacing a portion of the first dielectric layer over the vertical structure with a second dielectric layer; and

etching a portion of the first dielectric layer to expose the lateral surface of the vertical structure.

12. The method of claim 11, wherein replacing the portion of the first dielectric layer over the vertical structure with the second dielectric layer further comprises:

forming a first film layer over the first dielectric layer;

performing chemical mechanical polishing on the first film layer and stopping on the first dielectric layer;

etching a portion of the first dielectric layer to expose a top surface of the vertical structure and to form a recess;

forming the second dielectric layer over the first film layer and in the recess;

performing chemical mechanical polishing on the second dielectric layer and stopping on the first film layer; and

etching the first film layer.

13. The method of claim 12, wherein forming the first film layer over the first dielectric layer comprises forming the first film layer with at least one of poly and an ashable amorphous carbon film.

14. The method of claim 12, wherein forming the second dielectric layer over the first film layer and in the recess further comprises forming the second dielectric layer with at least one of oxide, SiN, SiON, SiC, SiCN and SiOCN.

15. The method of claim 11, wherein laterally etching the sidewall of the first dielectric layer further comprises laterally etching the sidewall of the first dielectric layer by using a plasma etching process with a lateral power.

16. The method of claim 11, further comprising forming a third dielectric layer over the substrate.

17. The method of claim 11, wherein forming the first dielectric layer over the vertical structure and the substrate further comprises forming the first dielectric layer with at least one of oxide, SiN, SiON, SiC, SiCN and SiOCN.

18. The method of claim 11, wherein forming the first dielectric layer over the vertical structure and the substrate further comprises forming the first dielectric layer having a thickness of about 5-40 nanometers.

19. The method of claim 11, wherein providing the vertical structure over the substrate further comprises providing the vertical structure having a source layer and a channel layer.

20. The method of claim 11, wherein providing the vertical structure over the substrate further comprises providing the vertical structure having a source layer, a drain layer and a channel layer.