Corner layout for high voltage semiconductor devices

• US 9,224,852 B2
• Filed: 07/30/2012
• Issued: 12/29/2015
• Est. Priority Date: 08/25/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Guan, Lingpeng, Bhalla, Anup
• Primary Examiner(s): Nicely, Joseph C
• Application Number:
  US13/561,500
• Publication Number:
  US 20140027819A1
• Time in Patent Office: 1,247 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell in the first array is spaced a uniform distance from the nearest termination device structure. In the second subset, the ends of striped cells proximate a corner of the active cell region are configured to maximize breakdown voltage by spacing the ends of each striped cell a non-uniform distance from the nearest termination device structure. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A semiconductor device comprising:

a doped layer;

an active cell region formed in the doped layer, the active cell region having a plurality of active cell device structures arranged in striped cell arrays, wherein each striped cell array having a first end and a second end; and

a termination region having a plurality of termination device structures formed in the doped layer surrounding the active cell region,

wherein a first subset of the striped cell arrays are configured to maximize a breakdown voltage of the semiconductor device by having the first and second ends of each striped cell array in the first subset spaced a uniform distance from a nearest termination device structure; and

wherein a second subset of the striped cell arrays proximate to a corner region of the active cell region are configured to maximize the breakdown voltage by spacing the first and second ends of each striped cell array in the second subset a non-uniform distance from the nearest termination device structure, wherein the second subset of the striped cell arrays include arcuate end portions in the shape of quarter circles.

2. The device of claim 1, wherein the first and second ends of each of the striped cell arrays in the second subset are spaced a uniform distance from a nearest striped cell array in the first subset.

3. The device of claim 1, wherein the first and second ends of an outermost striped cell array of the second subset are spaced further away from the nearest termination device structure than the first and second ends of the striped cell arrays in the first subset.

4. The device of claim 1, wherein the termination device structures proximate the corner region include arcuate portions that are concentric with the arcuate end portions of the second subset of the striped cell arrays.

5. The device of claim 1, wherein the termination device structures are arranged in concentric ring arrays.

6. The device of claim 5, wherein an innermost ring array of termination device structures has a plurality of spurs extending inward towards the active cell region and wherein a distance between each of the spurs and a nearby striped cell array in the second subset is configured to maximize the breakdown voltage of the device.

7. A method of forming a semiconductor device, comprising:

forming a doped layer;

forming an active cell region in the doped layer, the active cell region having a plurality of active cell device structures arranged as striped cell arrays, each striped cell array having a first end and a second end; and

forming a termination region having a plurality of termination device structures formed in the doped layer surrounding the active cell region,

wherein a first subset of the striped cell arrays are configured to maximize a breakdown voltage of the semiconductor device by having the first and second ends of each striped cell array spaced a uniform distance from a nearest termination device structure; and

wherein a second subset of the striped cell arrays proximate to a corner region of the active cell region are configured to maximize the breakdown voltage by spacing the first and second ends of each striped cell array in the second subset a non-uniform distance from the nearest termination device structure, wherein the striped cell arrays of the second subset include arcuate end portions configured as concentric quarter circles.

8. The method of claim 7, wherein the first and second ends of each of the striped cell array in the second subset include are spaced a uniform distance from a nearest striped cell array in the first subset.

9. The method of claim 7, wherein the first and second ends of an outermost striped cell array of the second subset are formed further away from the nearest termination device structure than the first and second ends of the other striped cell arrays in the first subset.

10. The method of claim 7, wherein the termination device structures proximate the corner region include arcuate portions that are concentric with the arcuate end portions of the striped cell arrays of the second subset.

11. The method of claim 7, wherein the termination device structures are arranged in concentric ring arrays.

12. The method of claim 11, wherein an innermost ring array of termination device structures has a plurality of spurs extending inward towards the active cell region, wherein a distance between each of the spurs and a nearby striped cell array in the second subset is configured to maximize the breakdown voltage of the device.