Trench gated power device with multiple trench width and its fabrication process
First Claim
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1. A semiconductor device, comprising:
- a semiconductor mass;
gate electrodes, and shield electrodes beneath said gate electrodes, in first trenches in said semiconductor mass, and field plate electrodes in second trenches in said semiconductor mass;
wherein said first trenches and said second trenches both extend into a first surface of said semiconductor mass, and all have substantially the same depth;
wherein said first and said second trenches each have a top portion which is wider than a middle portion thereof which has substantially vertical sidewalls, and also a bottom portion which is narrower than said middle portion; and
wherein said gate electrodes, but not said field plate electrodes, are connected directly to receive a gate drive waveform;
a first-conductivity-type source region, in said semiconductor mass, near said first trenches, and a second-conductivity-type body region adjacent said first trenches, and a second-conductivity-type body contact region surrounding and self-aligned to said second trenches; and
a first-conductivity-type drain region at a second surface of said semiconductor mass;
whereby, in the ON state, voltage applied to said gate electrode controls majority carrier emission from said source, to thereby allow current conduction between said source and said drain; and
whereby said field plate electrodes affect isopotential contours, in the OFF state, to increase the breakdown voltage between said source and said drain.
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Abstract
Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps.
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Citations
9 Claims
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1. A semiconductor device, comprising:
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a semiconductor mass; gate electrodes, and shield electrodes beneath said gate electrodes, in first trenches in said semiconductor mass, and field plate electrodes in second trenches in said semiconductor mass;
wherein said first trenches and said second trenches both extend into a first surface of said semiconductor mass, and all have substantially the same depth;
wherein said first and said second trenches each have a top portion which is wider than a middle portion thereof which has substantially vertical sidewalls, and also a bottom portion which is narrower than said middle portion; and
wherein said gate electrodes, but not said field plate electrodes, are connected directly to receive a gate drive waveform;a first-conductivity-type source region, in said semiconductor mass, near said first trenches, and a second-conductivity-type body region adjacent said first trenches, and a second-conductivity-type body contact region surrounding and self-aligned to said second trenches; and a first-conductivity-type drain region at a second surface of said semiconductor mass; whereby, in the ON state, voltage applied to said gate electrode controls majority carrier emission from said source, to thereby allow current conduction between said source and said drain; and
whereby said field plate electrodes affect isopotential contours, in the OFF state, to increase the breakdown voltage between said source and said drain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification