Lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a below source isolation region and a method of forming the LDMOSFET

• US 9,224,858 B1
• Filed: 07/29/2014
• Issued: 12/29/2015
• Est. Priority Date: 07/29/2014
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Camillo-Castillo, Renata, Sharma, Santosh, Shi, Yun, Stamper, Anthony K.
• Primary Examiner(s): Luke, Daniel
• Application Number:
  US14/445,101
• Time in Patent Office: 518 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

Disclosed are a field effect transistor (FET) (e.g., a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET)) and a method of forming the FET. In the FET, an etch stop pad is on a semiconductor substrate (e.g., a P-type silicon substrate). A semiconductor layer (e.g., a silicon layer) is also on the substrate and extends laterally over the etch stop pad. A first well region (e.g., an N-well region) extends through the semiconductor layer into the substrate such that it contains the etch stop pad. A second well region (e.g., a P-well region) is in the first well region aligned above the etch stop pad. A source region (e.g., a N-type source region) is in the second well region. A buried isolation region (e.g., a buried air-gap isolation region) is within the first well region aligned below the etch stop pad so as to limit vertical capacitor formation.

Claims

1. A field effect transistor comprising:

a semiconductor substrate having a first type conductivity;

an etch stop pad on said semiconductor substrate;

a semiconductor layer on said semiconductor substrate positioned laterally immediately adjacent to said etch stop pad and further extending over said etch stop pad;

a first well region extending from a top surface of said semiconductor layer into said semiconductor substrate such that said etch stop pad is contained within said first well region, said first well region having a second type conductivity different from said first type conductivity;

a second well region within said first well region at said top surface of said semiconductor layer and aligned above said etch stop pad, said second well region having said first type conductivity;

a source region within said second well region at said top surface of said semiconductor layer;

a drain region within said first well region at said top surface of said semiconductor layer and separated from said second well region, said source region and said drain region each having said second type conductivity; and

,

a buried isolation region within said first well region aligned below said etch stop pad.

2. The field effect transistor of claim 1, said etch stop pad comprising any of a silicon dioxide pad, a silicon nitride pad, and a silicon germanium pad.

3. The field effect transistor of claim 1, said buried isolation region comprising a buried air-gap isolation region comprising a cavity filled with any one of air alone and a combination of air and at least one isolation layer.

4. The field effect transistor of claim 1, further comprising:

an opening extending from a top surface of said semiconductor layer through said second well region and said etch stop pad to said buried isolation region, said opening having walls;

a protective liner lining said walls; and

,

an isolation layer plugging said opening.

5. The field effect transistor of claim 1, further comprising a gate structure on said top surface of said semiconductor layer between said source region and said drain region, said gate structure having a first sidewall and a second sidewall opposite said first sidewall, said first sidewall being a first distance from said source region and said second sidewall being a second distance from said drain region, said second distance being greater than said first distance.

6. The field effect transistor of claim 5, further comprising:

a third well region in said first well region at said top surface of said semiconductor layer, containing said drain region and extending laterally below said gate structure toward said second well region, said third well region having said second type conductivity at a lower conductivity level than said drain region and at a higher conductivity level than said first well region; and

,

a trench isolation region in said third well region at said top surface of said semiconductor layer, said trench isolation region being positioned immediately adjacent to said drain region and extending laterally below said gate structure toward said second well region.

7. A field effect transistor comprising:

a silicon substrate having a P-type conductivity;

an etch stop pad on said silicon substrate;

a silicon layer on said silicon substrate positioned laterally immediately adjacent to said etch stop pad and further extending over said etch stop pad;

a first well region extending from a top surface of said silicon layer into said silicon substrate such that said etch stop pad is contained within said first well region, said first well region having a N-type conductivity;

a second well region within said first well region at said top surface of said silicon layer and aligned above said etch stop pad, said second well region having said P-type conductivity;

a source region within said second well region at said top surface of said silicon layer;

a drain region within said first well region at said top surface of said silicon layer and separated from said second well region, said source region and said drain region each having said N-type conductivity; and

,

a buried isolation region within said first well region aligned below said etch stop pad.

8. The field effect transistor of claim 7, said etch stop pad comprising any of a silicon dioxide pad, a silicon nitride pad, and a silicon germanium pad.

9. The field effect transistor of claim 7, said buried isolation region comprising a buried air-gap isolation region comprising a cavity filled with any one of air alone and a combination of air and at least one isolation layer.

10. The field effect transistor of claim 7, further comprising:

an opening extending from a top surface of said silicon layer through said second well region and said etch stop pad to said buried isolation region, said opening having walls;

a protective liner lining said walls; and

,

an isolation layer plugging said opening.

11. The field effect transistor of claim 7, further comprising a gate structure on said top surface of said silicon layer between said source region and said drain region, said gate structure having a first sidewall and a second sidewall opposite said first sidewall, said first sidewall being a first distance from said source region and said second sidewall being a second distance from said drain region, said second distance being greater than said first distance.

12. The field effect transistor of claim 11, further comprising:

a third well region in said first well region at said top surface of said silicon layer, containing said drain region and extending laterally below said gate structure toward said second well region, said third well region having said N-type conductivity at a lower conductivity level than said drain region and at a higher conductivity level than said first well region; and

,

a trench isolation region in said third well region at said top surface of said silicon layer, said trench isolation region being positioned immediately adjacent to said drain region and extending laterally below said gate structure toward said second well region.

13. A method of forming a field effect transistor, said method comprising:

forming an etch stop pad on a semiconductor substrate having a first type conductivity;

forming a semiconductor layer on said semiconductor substrate positioned laterally adjacent to said etch stop pad and further extending over said etch stop pad;

forming a first well region extending from a top surface of said semiconductor layer into said semiconductor substrate such that said first well region has a second type conductivity different from said first type conductivity and such that said first well region contains said etch stop pad;

forming a second well region within said first well region at said top surface of said semiconductor layer and aligned above said etch stop pad, said second well region having said first type conductivity;

forming a gate structure on a top surface of said semiconductor layer above said first well region and overlapping an edge portion of said second well region;

forming a source region and a drain region each having said second type conductivity, said source region being formed within said second well region at said top surface of said semiconductor layer adjacent to a first sidewall of said gate structure and said drain region being formed within said first well region at said top surface of said semiconductor layer adjacent to a second sidewall of said gate structure opposite said first sidewall; and

,

forming a buried isolation region within said first well region and aligned below said etch stop pad and said second well region.

14. The method of claim 13, said forming of said etch stop pad comprising:

depositing an etch stop layer comprising any one of a dielectric material and a semiconductor material that is different from said semiconductor substrate; and

,

patterning said etch stop layer to form said etch stop pad.

15. The method of claim 13, said forming of said semiconductor layer comprising epitaxially depositing said semiconductor layer on said semiconductor substrate and over said etch stop pad.

16. The method of claim 13, said forming of said buried isolation region comprising:

forming an opening extending from said top surface of said semiconductor layer through said second well region and said etch stop pad to said semiconductor substrate;

lining walls of said opening with a protective liner;

etching said semiconductor substrate at a bottom of said opening to form a cavity below said etch stop pad, said etching being selective for said semiconductor substrate over said etch stop pad; and

,

depositing an isolation layer into said opening.

17. The method of claim 16, said etching being stopped before said cavity extends laterally beyond said etch stop pad.

18. The method of claim 16, said isolation layer plugging said opening without entirely filling said cavity such that said buried isolation region comprises a buried air-gap isolation region comprising said cavity filled with any one of air alone and a combination of air and said isolation layer.

19. The method of claim 13, said gate structure and said source region and said drain region being formed such that said first sidewall of said gate structure is a first distance from said source region and such that said second sidewall of said gate structure is a second distance from said drain region, said second distance being greater than said first distance.

20. The method of claim 13, further comprising:

forming, at said top surface of said semiconductor layer, a trench isolation region; and

,

forming a third well region in said first well region around said trench isolation region,

said drain region subsequently being formed within said third well region such that said trench isolation region is positioned laterally between said drain region and said second well region,

said gate structure subsequently being formed on said top surface of said semiconductor layer with said first sidewall above said second well region and said second sidewall above said trench isolation region, and

said first well region, said third well region and said drain region being formed so as to have said second type conductivity and so that said third well region has a higher conductivity level than said first well region and a lower conductivity level than said drain region.