Comparator for synchronous rectification and method of operation

• US 9,225,247 B2
• Filed: 03/31/2014
• Issued: 12/29/2015
• Est. Priority Date: 03/31/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Berens, Michael T.
• Primary Examiner(s): Laxton, Gary L
• Application Number:
  US14/230,734
• Publication Number:
  US 20150280562A1
• Time in Patent Office: 638 Days
• Field of Search: 327/56, 327/62, 327/65, 327/72, 327/77, 323/222, 323/282
• US Class Current: 1/1
• CPC Class Codes: H02M 1/0054 Transistor switching losses periodically suspending operation of switching converter in low power mode H02M1/0035
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A boost converter includes a comparator having first and second gain stages that operate in compare and auto-zero modes. The comparator measures voltage drop across a P-channel transistor to determine when current through an inductor reaches zero. When the inductor current reaches zero, the P-channel transistor becomes inactive to prevent a reduction in efficiency caused by allowing negative inductor current to draw current from a load. The comparator is then placed in a low power state. When the comparator is not in a compare mode, the comparator can operate in an auto-zero mode to cancel offset when measuring the input of the comparator.

Claims

1. A boost converter, comprising:

a comparator having;

a first and second N-channel transistors, a source of the first and second N-channel transistors coupled to ground, a drain of the first and second N-channel transistors coupled to a respective control gate of the first and second N-channel transistors;

a switch connected between the drain and the control gate of the second N-channel transistor and operated by a N-gate signal,

a first P-channel transistor having a drain coupled to the drain of the second N-channel transistor and a source coupled to a drain of a third P-channel transistor and a drain of a fourth P-channel transistor,

the third P-channel transistor includes a control gate coupled to a complimentary N-gate signal, and a source coupled to an output voltage of the converter,

the fourth P-channel transistor includes a control gate coupled to a P-gate signal, and a source coupled to a coil voltage,

a second P-channel transistor having a drain coupled to the drain of the first N-channel transistor and a source coupled to a drain of a fifth P-channel transistor and a drain of a sixth P-channel transistor,

the fifth P-channel transistor includes a control gate coupled to the P-gate signal, and a source coupled to the VOUT of the converter, and

the sixth P-channel transistor includes a control gate coupled to the complimentary N-gate signal, and a source coupled to the VOUT of the converter.

2. The converter of claim 1, further comprising a capacitor coupled between the control gates of the first and second N-channel transistors.

3. The converter of claim 1, further comprising a first resistor coupled between the source of the first P-channel transistor and the drain of the fourth P-channel transistor.

4. The converter of claim 1, further comprising:

an inductor having a first terminal coupled to a first node (106), the coil voltage being measurable at the first node;

a first switch having a control terminal coupled to a P-gate prime signal, a first terminal coupled to the first node, and a second terminal coupled to the VOUT;

the comparator having an inverting input coupled to the first terminal of the first switch and a non-inverting input coupled to the second terminal of the first switch;

the P-gate prime signal being set based on an output voltage of the comparator to place the first switch in an inactive mode when current through the inductor is less than or equal to zero.

5. The converter of claim 4, further comprising:

a logic OR gate having a first input coupled to the P-gate signal, a second input coupled to the output voltage of the comparator and an output coupled to provide the P-gate prime signal to the control gate of the first switch.

6. The converter of claim 4, wherein the P-gate signal is set HIGH when current through the inductor is increasing to a peak current and LOW a portion of time when current through the inductor is decreasing from the peak current or is zero.

7. The converter of claim 4, wherein the complementary N-gate signal is set LOW during an auto-zero mode of the comparator and HIGH during a compare mode of the comparator.

8. The converter of claim 1, further comprising:

a third N-channel transistor;

a sixth N-channel transistor;

a seventh P-channel transistor;

the sixth N-channel transistor having a source coupled ground, a drain coupled to a source of the third N-channel transistor, and a control gate coupled to an enable signal;

the third N-channel transistor having a drain coupled to a drain of the seventh P-channel transistor and a control gate coupled to the drain of the first N-channel transistor;

the seventh P-channel transistor having a source coupled to the VOUT of the converter and a control gate coupled to the drain of the seventh P-channel transistor;

a fourth N-channel transistor;

a fifth N-channel transistor;

an eighth P-channel transistor;

the fifth N-channel transistor having a source coupled to ground, a drain coupled to a source of the fourth N-channel transistor, and a control gate coupled to an enable signal;

the fourth N-channel transistor having a drain coupled to a drain of the eighth P-channel transistor and a control gate coupled to the drain of the second N-channel transistor;

the eighth P-channel transistor having a source coupled to the VOUT of the converter and a control gate coupled to the control gate of the seventh P-channel transistor.

9. The converter of claim 8, further comprising:

a current source;

a ninth P-channel transistor;

a tenth P-channel transistor;

an eleventh P-channel transistor;

a twelfth P-channel transistor;

a seventh N-channel transistor;

a set-reset latch having a reset input coupled to the N-gate signal, a set input coupled between the drain of the eighth P-channel transistor and the drain of the fourth N-channel transistor, and an output coupled to provide the output voltage of the comparator;

a logic AND gate having a first input coupled to the output voltage of the comparator, a second input coupled to a complementary P-gate signal, and an output coupled to provide a low power signal, a complement of the low power signal is coupled to a control gates of the eleventh and twelfth P-channel transistors;

the current source having one terminal coupled to ground and another terminal coupled to a drain of the ninth P-channel transistor;

the ninth P-channel transistor having a control gate coupled to control gates of the first and second P-channel transistors and the drain of the ninth P-channel transistor, and a source coupled to a drain of the tenth P-channel transistor;

the tenth P-channel transistor having a source coupled to the VOUT of the converter and a control gate coupled to ground;

the eleventh P-channel transistor having a drain coupled to the control gates of the first, second, and ninth P-channel transistors, and a source coupled to the VOUT;

the twelfth P-channel transistor having a drain coupled to the control gates of the seventh and eighth P-channel transistors, and a source coupled to the VOUT of the converter;

the seventh N-channel transistor having a drain coupled to the set terminal of the set-reset latch, a source coupled to ground, and a control gate coupled to the low power signal.

10. The converter of claim 9, further comprising:

a logic AND gate having a first input coupled to the complimentary N-gate signal, a second input coupled to a complement of the low power signal, and an output coupled to provide the enable signal.

11. A DC-DC boost converter comprising:

an inductor having a first terminal coupled to a coil voltage;

a capacitor having a first terminal coupled to a second terminal of a switch and a second terminal coupled to ground;

a comparator having a first input coupled to the coil voltage and a second input coupled to ground, the comparator including;

a first diode-connected N-channel transistor;

a second diode-connected N-channel transistor having a switch coupled between a drain and a control gate;

a capacitor having a first terminal coupled to a control gate of the first diode-connected N-channel transistor and a second terminal coupled to the control gate of the second diode-connected N-channel transistor;

a first P-channel transistor having a drain coupled to a drain of the second diode-connected N-channel transistor;

a third P-channel transistor having a drain coupled to a source of the first P-channel transistor, a control gate coupled to a complementary N-gate signal and a source coupled to an output voltage of the converter;

a fourth P-channel transistor having a control gate coupled to a P-gate signal, a drain coupled to the source of the first P-channel transistor and a source coupled to the coil voltage;

a second P-channel transistor having a drain coupled to a drain of the second diode-connected N-channel transistor and a control gate coupled to a control gate of the first P-channel transistor;

a fifth P-channel transistor having a control gate coupled to the P-gate signal, a drain coupled to a source of the second P-channel transistor and a source coupled to the VOUT;

a sixth P-channel transistor having a drain coupled to the source of the second P-channel transistor, a control gate coupled to a complementary N-gate signal and a source coupled to the VOUT.

12. The converter of claim 11, further comprising a first resistor coupled between the source of the first P-channel transistor and the drain of the fourth P-channel transistor.

13. The converter of claim 11, wherein the first and second P-channel transistors and the first and second N-channel transistors are part of a first gain stage of the comparator.

14. The converter of claim 11, further comprising:

the first switch having a control terminal coupled to a P-gate prime signal, and a first terminal coupled to the coil voltage;

the comparator having an inverting input coupled to the first terminal of the first switch and a non-inverting input coupled to the second terminal of the first switch.

15. The converter of claim 14, wherein the P-gate prime signal is set based on an output voltage (RECT) of the comparator to place the first switch in an inactive mode when current through the inductor is less than or equal to zero.

16. The converter of claim 14, wherein the complementary N-gate signal is set LOW when the converter is in an auto-zero mode and set HIGH when the converter is in a compare mode.

17. The converter of claim 11, wherein the P-gate signal is set HIGH during an auto-zero mode of the comparator and LOW during a compare mode of the comparator.

18. The converter of claim 11, further comprising:

a second gain stage in the comparator including;

a third N-channel transistor;

a fourth N-channel transistor;

a seventh P-channel transistor; and

an eighth P-channel transistor;

a fifth N-channel transistor having a source coupled ground, a drain coupled to a source of the fourth N-channel transistor, and a control gate coupled to an enable signal;

a sixth N-channel transistor having a source coupled to ground, a drain coupled to a source of the third N-channel transistor, and a control gate coupled to the enable signal;

the third N-channel transistor having a drain coupled to a drain of the seventh P-channel transistor and a control gate coupled to the drain of the first N-channel transistor;

the seventh P-channel transistor having a source coupled to the VOUT and a control gate coupled to the drain of the seventh P-channel transistor;

the fourth N-channel transistor having a drain coupled to a drain of the eighth P-channel transistor and a control gate coupled to the drain of the second N-channel transistor;

the eighth P-channel transistor having a source coupled to the VOUT and a control gate coupled to the control gate of the seventh P-channel transistor.

19. The converter of claim 18, further comprising:

a current source;

a ninth P-channel transistor;

a tenth P-channel transistor;

an eleventh P-channel transistor;

a twelfth P-channel transistor;

a seventh N-channel transistor;

a set-reset latch having a reset input coupled to the N-gate signal, a set input coupled between the drain of the eighth P-channel transistor and the drain of the fourth N-channel transistor, and an output coupled to provide an output voltage (RECT) of the comparator;

a logic gate having a first input coupled to the output voltage of the comparator, a second input coupled to a complementary P-gate signal, and an output coupled to provide a low power signal;

the current source having one terminal coupled to ground and another terminal coupled to a drain of the ninth P-channel transistor;

the ninth P-channel transistor having a control gate coupled to the control gates of the first and second P-channel transistors and a source coupled to a drain of the tenth P-channel transistor;

the tenth P-channel transistor having a control gate coupled to ground and a source coupled to the VOUT;

the eleventh P-channel transistor having a drain coupled to the control gates of the first, second, and ninth P-channel transistors;

the twelfth P-channel transistor having a drain coupled to the control gates of the seventh and eighth P-channel transistors, and a source coupled to the VOUT;

the seventh N-channel transistor having a drain coupled to the set terminal of the set-reset latch, and a source coupled to ground.

20. The converter of claim 19, further comprising:

a logic gate having a first input coupled to the complementary N-gate signal, a second input coupled to a complement of the low power signal, and an output coupled to provide an enable signal.