High-efficiency, low-power power supply circuit

• US 9,225,260 B2
• Filed: 08/08/2012
• Issued: 12/29/2015
• Est. Priority Date: 08/08/2012
• Status: Expired due to Fees

• Current Assignee: IXYS, LLC (Littelfuse Incorporated)
• Original Assignee: IXYS Corporation (Littelfuse Incorporated)
• Inventors: Neyman, Leonid A.
• Primary Examiner(s): Ngo, Brian
• Application Number:
  US13/569,458
• Publication Number:
  US 20140043878A1
• Time in Patent Office: 1,238 Days
• Field of Search: 320/106, 320/166, 323/282, 323/284, 323/285, 323/286, 323/351
• US Class Current: 1/1
• CPC Class Codes: H02J 7/345 using capacitors as storage or buffering devices
• CPC Class Codes: H02M 1/0006 Arrangements for supplying an adequate voltage to the control circuit of converters
• CPC Class Codes: H02M 7/2176 comprising a passive stage to generate a rectified sinusoidal voltage and a controlled switching element in series between such stage and the output

Abstract

A power supply circuit includes a rectifier, a charging circuit, and a storage capacitor. An AC signal is rectified by the rectifier thereby generating a rectified signal V_R between a V_R node and a GND node. The capacitor is coupled between an output voltage V_O node and the GND node. If V_R is greater than a first predetermined voltage V_P then the V_O node is decoupled from the V_R node. If V_R is below V_P then the charging circuit supplies a substantially constant charging current from the V_R node, through the charging circuit, to the V_O node, and to the capacitor, provided that V_O on the capacitor is below a second predetermined voltage V_O(MAX) and provided that V_R is adequately high with respect to V_O. Due to the charging current, the voltage V_O on the storage capacitor is restored to the desired second predetermined voltage.

Claims

1. A circuit for charging a capacitor, wherein the capacitor has a first lead coupled to an output voltage V_O node, and wherein the capacitor has a second lead coupled to a GND node, the circuit comprising:

a full wave bridge rectifier that supplies a rectified voltage signal (V_R) onto a V_R node, and that supplies a ground potential GND onto the GND node; and

a charging circuit that;

     1) decouples the V_O node from the V_R node when V_R is greater than a first predetermined voltage V_P and,

     2) supplies a charging current (I_CHARGE) from the V_R node and onto the V_O node when V_R is less than V_P provided that V_O is less than a second predetermined voltage V_O(MAX) and provided that V_R is greater than V_O, wherein the second predetermined voltage V_O(MAX) is determined by a Zener voltage of a Zener diode and a source-to-gate voltage of a depletion mode field effect transistor (dep-FET).

2. The circuit of claim 1, wherein the charging circuit comprises:

a zener diode, and wherein the zener diode determines the second predetermined voltage V_O(MAX) of the output voltage signal V_O.

3. The circuit of claim 1, wherein the charging circuit comprises:

a switch through which I_CHARGE flows from the V_R node to the V_O node; and

a zener diode that determines the second predetermined voltage V_O(MAX) of the output voltage signal V_O.

4. The circuit of claim 3, wherein the switch is a field effect transistor, and wherein the zener diode is coupled via a resistor to a gate of the switch.

5. The circuit of claim 3, wherein the switch is a depletion mode field effect transistor (dep-FET).

6. The circuit of claim 1, wherein the V_R signal has a maximum value V_R(MAX) of more than approximately +150 volts, and wherein V_R has a minimum value V_R(MIN) that is greater than zero volts.

7. The circuit of claim 1, wherein there is less than approximately 0.5 microfarads of capacitance on the V_R node.

8. The circuit of claim 1, wherein the charging circuit supplies I_CHARGE onto the V_O node through a depletion mode field effect transistor (dep-FET), wherein the dep-FET has a body diode, and wherein a cathode of the body diode is coupled to the V_R node.

9. The circuit of claim 1, wherein the charging circuit comprises:

a depletion mode field effect transistor (dep-FET) through which the I_CHARGE flows from the V_R node to the V_O node; and

a voltage detector circuit that detects when V_R is greater than the first predetermined voltage V_P and that causes the dep-FET to be turned off when V_R is greater than the first predetermined voltage V_P.

10. The circuit of claim 9, wherein the voltage detector circuit comprises:

a reference voltage generator;

a comparator having a first input lead, a second input lead, and an output lead, wherein the first input lead of the comparator is coupled via a voltage divider to the V_R node, and wherein the second input lead of the comparator is coupled to receive a reference voltage from the reference voltage generator; and

a switch that receives a control signal from the output lead of the comparator, wherein when the switch is on a current can flow from the gate of the dep-FET to the GND node through the switch.

11. The circuit of claim 1, wherein the charging circuit comprises a comparator, wherein the comparator has a supply voltage input lead, and wherein the supply voltage input lead is coupled to the V_R node so that the comparator is powered by the V_R node.

12. The circuit of claim 1, wherein the circuit is a power supply integrated circuit, the circuit further comprising:

a first AC input terminal that is coupled to a first lead of the full wave bridge rectifier;

a second AC input terminal that is coupled to a second lead of the full wave bridge rectifier;

a third terminal that is coupled to and is a part of the GND node; and

a fourth terminal that is coupled to and is a part of the V_O node, wherein the first, second, third and fourth terminals are terminals of the power supply integrated circuit.

13. The circuit of claim 1, wherein the circuit is a packaged integrated circuit device, wherein the capacitor is a part of the packaged integrated circuit device, the circuit further comprising:

a first AC input terminal that is coupled to a first lead of the full wave bridge rectifier;

a second AC input terminal that is coupled to a second lead of the full wave bridge rectifier;

a third terminal that is coupled to and is a part of the GND node; and

a fourth terminal that is coupled to and is a part of the V_O node, wherein the first, second, third and fourth terminals are terminals of the packaged integrated circuit device.

14. The circuit of claim 13, wherein the full wave bridge rectifier and the charging circuit are parts of a first integrated circuit, the circuit further comprising:

a second integrated circuit that is a part of the packaged integrated circuit device, wherein a supply voltage input terminal of the second integrated circuit is coupled to the fourth terminal, and wherein a ground terminal of the second integrated circuit is coupled to the third terminal.

15. The circuit of claim 1, wherein the charging current supplied from the V_R node and onto the V_O node is a substantially constant charging current.

16. A method comprising:

(a) using a full wave bridge rectifier to rectify AC voltage signals and thereby generating a full wave rectified signal V_R, wherein V_R is present on a V_R node, and wherein V_R is a periodic signal and has a cycle, and wherein V_R is at times during the cycle greater than a predetermined voltage V_P and at other times during the cycle is less than the predetermined voltage V_P;

(b) providing a capacitor between an output voltage V_O node and a ground potential GND node;

(c) if V_R has a voltage greater than V_P then decoupling the V_R node from the output voltage V_O node; and

(d) if V_R has a voltage less than the V_P then supplying a substantially constant charging current from the V_R node and onto the V_O node provided that a magnitude of a voltage signal V_O on the V_O node is below a second predetermined voltage and provided that a magnitude of V_R is greater than the magnitude of V_O on the V_O node, wherein the second predetermined voltage is determined by a Zener voltage of a Zener diode and a source-to-gate voltage of a depletion mode field effect transistor (dep-FET).

17. The method of claim 16, wherein in (d) the substantially constant charging current flows from the V_R node, through a depletion mode field effect transistor, and to the V_O node.

18. A circuit for charging a capacitor, wherein the capacitor has a first lead coupled to an output voltage V_O node, and wherein the capacitor has a second lead coupled to a GND node, the circuit comprising:

a rectifier that supplies a rectified voltage signal (V_R) onto a V_R node; and

means for decoupling the V_O node from the V_R node when V_R is greater than a first predetermined voltage V_P such that no current flows from the V_R node to the V_O node, and wherein the means is also for supplying a charging current (I_CHARGE) from the V_R node and onto the V_O node when V_R is less than V_P provided that V_O is less than a second predetermined voltage V_O(MAX) and provided that V_R is greater than V_O, wherein the second predetermined voltage V_O(MAX) is determined by a Zener voltage of a Zener diode and a source-to-gate voltage of a depletion mode field effect transistor (dep-FET).

19. The circuit of claim 18, wherein the means comprises a depletion mode field effect transistor through which the charging current flows.

20. The circuit of claim 18, wherein the means comprises a switch through which the charging current flows, and wherein the means further comprises a voltage detector circuit that controls the switch to be open when V_R is greater than V_P.