Semiconductor device, driving method thereof, and electronic appliance

• US 9,225,329 B2
• Filed: 03/02/2015
• Issued: 12/29/2015
• Est. Priority Date: 03/07/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kozuma, Munehiro, Ikeda, Takayuki, Kurokawa, Yoshiyuki, Aoki, Takeshi, Nakagawa, Takashi
• Primary Examiner(s): Taningco, Alexander H
• Assistant Examiner(s): Correa, Nelson
• Application Number:
  US14/635,087
• Publication Number:
  US 20150256177A1
• Time in Patent Office: 302 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/16 Constructional details or arrangements
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A semiconductor device in which operation delay due to stop and restart of the supply of a power supply potential is suppressed is provided. Potentials corresponding to data held in first and second nodes while the supply of a power supply potential is continued are backed up in third and fourth nodes while the supply of the power supply potential is stopped. After the supply of the power supply potential is restarted, data are restored to the first and second nodes by utilizing a change in channel resistance of a transistor whose gate is electrically connected to the third or fourth node. Note that shoot-through current is suppressed at the time of data restoration by electrically disconnecting the power supply potential and the first or second node from each other.

Claims

1. A semiconductor device comprising:

first to third circuits,

wherein the first circuit comprises first and second nodes, first and second transistors, and first and second wirings,

wherein the second circuit comprises third to eighth transistors, third to fourth nodes, and a third wiring,

wherein the third circuit comprises first and second NAND circuits and first and second inverter circuits,

wherein the first node is capable of holding one of a first potential and a second potential,

wherein the second node is capable of holding the other of the first potential and the second potential,

wherein the first transistor is capable of controlling electrical continuity between the second node and the first wiring,

wherein the second transistor is capable of controlling electrical continuity between the first node and the second wiring,

wherein the first and second wirings are supplied with the first potential,

wherein the first node is electrically connected to the third node via the third transistor,

wherein the first node is electrically connected to the third wiring via the seventh and eighth transistors,

wherein the second node is electrically connected to the fourth node via the sixth transistor,

wherein the second node is electrically connected to the third wiring via the fourth and fifth transistors,

wherein a gate of the fourth transistor is electrically connected to the third node,

wherein a gate of the seventh transistor is electrically connected to the fourth node,

wherein a first signal is input to a gate of the fifth transistor and a gate of the eighth transistor,

wherein the third wiring is supplied with the second potential,

wherein the first signal is input to a first input terminal of the first NAND circuit,

wherein a second input terminal of the first NAND circuit is electrically connected to the third node,

wherein an output terminal of the first NAND circuit is electrically connected to a gate of the first transistor via the first inverter circuit,

wherein the first signal is input to a first input terminal of the second NAND circuit,

wherein a second input terminal of the second NAND circuit is electrically connected to the fourth node,

wherein an output terminal of the second NAND circuit is electrically connected to a gate of the second transistor via the second inverter circuit, and

wherein the third and sixth transistors each comprise an oxide semiconductor in a channel formation region.

2. The semiconductor device according to claim 1,

wherein the third node is capable of holding the potential supplied to the first node while a supply of a power supply potential to the first to third circuits is stopped, and

wherein the fourth node is capable of holding the potential supplied to the second node while the supply of the power supply potential to the first to third circuits is stopped.

3. An electronic appliance comprising:

the semiconductor device according to claim 2; and

at least one of a display device, a microphone, a speaker, an operation key, and a housing.

4. An electronic appliance comprising:

the semiconductor device according to claim 1; and

at least one of a display device, a microphone, a speaker, an operation key, and a housing.

5. A semiconductor device comprising:

first to third circuits,

wherein the first circuit comprises first and second nodes, first and second transistors, and first and second wirings,

wherein the second circuit comprises first and second inverter circuits, third to eighth transistors, third to fourth nodes, and a third wiring,

wherein the third circuit comprises first and second NAND circuits and third and fourth inverter circuits,

wherein the first node is capable of holding one of a first potential and a second potential,

wherein the second node is capable of holding the other of the first potential and the second potential,

wherein the first transistor is capable of controlling electrical continuity between the second node and the first wiring,

wherein the second transistor is capable of controlling electrical continuity between the first node and the second wiring,

wherein the first and second wirings are supplied with the first potential,

wherein the first node is electrically connected to the third node via the first inverter circuit and the third transistor,

wherein the first node is electrically connected to the third wiring via the fourth and fifth transistors,

wherein the second node is electrically connected to the fourth node via the second inverter circuit and the sixth transistor,

wherein the second node is electrically connected to the third wiring via the seventh and eighth transistors,

wherein a gate of the fourth transistor is electrically connected to the third node,

wherein a gate of the seventh transistor is electrically connected to the fourth node,

wherein a first signal is input to a gate of the fifth transistor and a gate of the eighth transistor,

wherein the third wiring is supplied with the second potential,

wherein the first signal is input to a first input terminal of the first NAND circuit,

wherein a second input terminal of the first NAND circuit is electrically connected to the fourth node,

wherein an output terminal of the first NAND circuit is electrically connected to a gate of the first transistor via the third inverter,

wherein the first signal is input to a first input terminal of the second NAND circuit,

wherein a second input terminal of the second NAND circuit is electrically connected to the third node,

wherein an output terminal of the second NAND circuit is electrically connected to a gate of the second transistor via the fourth inverter circuit, and

wherein the third and sixth transistors each comprise an oxide semiconductor in a channel formation region.

6. The semiconductor device according to claim 5,

wherein the third node is capable of holding the potential supplied to the second node while a supply of a power supply potential to the first to third circuits is stopped, and

wherein the fourth node is capable of holding the potential supplied to the first node while the supply of the power supply potential to the first to third circuits is stopped.

7. An electronic appliance comprising:

the semiconductor device according to claim 6; and

at least one of a display device, a microphone, a speaker, an operation key, and a housing.

8. An electronic appliance comprising:

the semiconductor device according to claim 5; and

at least one of a display device, a microphone, a speaker, an operation key, and a housing.