Single supply level shifter with improved rise time and reduced leakage

• US 9,225,333 B2
• Filed: 02/21/2014
• Issued: 12/29/2015
• Est. Priority Date: 02/21/2014
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Purushothaman, Soman
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US14/186,849
• Publication Number:
  US 20150244372A1
• Time in Patent Office: 676 Days
• Field of Search: 326/68, 326/81, 326/83, 326/87
• US Class Current: 1/1
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A single supply level shifter converts an input logic level IN into level shifted OUT and OUT_X. An IN inverter generates level-shifted OUT at an OUT Node. IN is coupled at an INT Node to a V_DD supply rail, through an INT_Node PFET that controls the INT Node based on OUT_X. An OUT_X network includes a separate IN_X inverter (generating inverted IN independent of level shifting), and an OUT_X circuit that controls pull-up/down of an OUT_X Node to generate level-shifted OUT_X, receiving control inputs from both IN and IN_X inverters. The OUT_X circuit is a three FET stack: a pull-up/down PFET/NFET pair receives IN_X, and an OUT_X Node control PFET, coupled between the pull-up PFET and the OUT_X Node, receives OUT. Based on OUT and IN_X, the OUT_X circuit generates OUT_X as an inverted OUT (including supplying OUT_X to the INT_Node PFET to control the INT Node (including OUT pull-up).

Claims

1. A logic level shift circuit with a single voltage supply rail for level shifting an input logic signal IN with logic_—

0 and logic_—

1 states (IN=0 and IN=1) to a corresponding level shifted output logic signal that is one of OUT or OUT_X (corresponding to an inverted OUT), comprising;

an IN inverter circuit configured to receive IN at an IN Node, and provide OUT as an inverted IN at an OUT Node, the IN inverter coupled between an INT Node and a ground/reference;

an INT_Node PFET transistor source coupled to the supply rail and drain coupled to the INT Node, and controlled by an OUT_X control signal corresponding to OUT_X to provide INT Node pull-up in response to an OUT_X=0 control signal;

an OUT_X network configured to provide OUT_X as an inverted OUT at an OUT_X Node, including providing the OUT_X control signal to the INT_Node PFET, the OUT_X network including;

an IN_X inverter circuit configured to receive IN from the IN Node, and provide IN_X as an inverted IN at an IN_X Node;

OUT_X circuitry including

OUT_X Node pull-up/down circuitry including pull-up PFET and pull-down NFET transistors, gate coupled to the IN_X Node, the pull-up PFET source coupled to the supply rail, and the pull-down NFET drain coupled to the OUT_X Node and source coupled to the ground/reference; and

an OUT_X Node PFET transistor series coupled between the pull-up PFET and the OUT_X Node, and gate coupled to the OUT Node to receive OUT as an OUT control signal;

the OUT_X circuitry configured to control OUT_X based on IN_X and the OUT control signal, such that;

for IN=0, the OUT_X circuitry receives IN_X=1 at the pull-up/down PFET and NFET, and an OUT=1 control signal at the OUT_X_Node PFET, pulling down the OUT_X Node to OUT_X=0, and providing an OUT_X=0 control signal to the INT_Node PFET, which pulls-up the INT Node and as a result the OUT Node is pulled up to OUT=1, and

for IN=1, the OUT_X circuitry receives IN_X=0 at the pull-up/down PFET and NFET, and an OUT=0 control signal at the OUT_X_Node PFET, pulling up the OUT_X Node to OUT_X=1, and providing an OUT_X=1 control signal to the INT_Node PFET, terminating pull-up of the INT Node.

2. The circuit of claim 1, wherein the INT_Node PFET connects the INT Node to the supply rail, such that, in response to the OUT_X=1 control signal, the INT Node is disconnected from the supply rail.

3. The circuit of claim 1, wherein the IN inverter includes PFET and NFET transistors, gate coupled at the IN Node, and drain-coupled at the OUT Node, the PFET source coupled to the INT Node and the NFET source coupled to the ground/reference.

4. The circuit of claim 1, wherein the IN_X inverter includes PFET and NFET transistors, gate coupled to the IN Node, and drain-coupled at the IN_X Node, the PFET source coupled to the supply rail and the NFET source coupled to the ground/reference.

5. The circuit of claim 4, further comprising a diode connected PFET coupled between the supply rail and the PFET of the IN_X inverter, to reduce the supply voltage at the PFET source.

6. The circuit of claim 1, wherein the ground/reference comprises a circuit ground.

7. A logic level shifter with a single voltage supply rail for level shifting an input logic signal IN with logic_—

0 and logic_—

1 states (IN=0 and IN=1) to a corresponding level shifted output logic signal that is one of OUT or OUT_X (corresponding to an inverted OUT), comprising;

an IN inverter configured to receive IN at an IN Node, and provide OUT as an inverted IN at an OUT Node, the inverter including PFET and NFET transistors, gate coupled at the IN Node, and drain-coupled at the OUT Node, the PFET source coupled to an INT Node and the NFET source coupled to ground/reference;

an INT_Node PFET transistor source coupled to the supply rail and drain coupled to the INT Node, and controlled by an OUT_X control signal corresponding to OUT_X to provide INT Node pull-up in response to an OUT_X=0 control signal; and

an OUT_X network configured to provide OUT_X as an inverted OUT at an OUT_X Node, including providing the OUT_X control signal to the INT_Node PFET, the OUT_X network including;

an IN_X inverter circuit configured to receive IN from the IN Node, and provide IN_X as an inverted IN at an IN_X Node;

OUT_X circuitry including

OUT_X Node pull-up/down circuitry including pull-up PFET and pull-down NFET transistors, gate coupled to the IN_X Node, the pull-up PFET source coupled to the supply rail, and the pull-down NFET drain coupled to the OUT_X Node and source coupled to the ground/reference; and

an OUT_X Node PFET transistor series coupled between the pull-up PFET and the OUT_X Node, and gate coupled to the OUT Node to receive OUT as an OUT control signal;

the OUT_X circuitry configured to control OUT_X based on IN_X and the OUT control signal, such that;

for IN=0, the OUT_X circuitry receives IN_X=1 at the pull-up/down PFET and NFET, and an OUT=1 control signal at the OUT_X_Node PFET, pulling down the OUT_X Node to OUT_X=0, and providing an OUT_X=0 control signal to the INT_Node PFET, which pulls-up the INT Node and as a result the OUT Node is pulled up to OUT=1, and

for IN=1, the OUT_X circuitry receives IN_X=0 at the pull-up/down PFET and NFET, and an OUT=0 control signal at the OUT_X_Node PFET, pulling up the OUT_X Node to OUT_X=1, and providing an OUT_X=1 control signal to the INT_Node PFET, terminating pull-up of the INT Node.

8. The logic level shifter of claim 7, wherein the INT_Node PFET connects the INT Node to the supply rail, such that, in response to the OUT_X=1 control signal, the INT Node is disconnected from the supply rail.

9. The logic level shifter of claim 7, wherein the IN_X inverter includes PFET and NFET transistors, gate coupled to the IN Node, and drain-coupled at the IN_X Node, the PFET source coupled to the supply rail and the NFET source coupled to the ground/reference.

10. The logic level shifter of claim 9, further comprising a diode connected PFET coupled between the supply rail and the PFET of the IN_X inverter, to reduce the supply voltage at the PFET source.

11. The logic level shifter of claim 7, wherein the ground/reference comprises circuit ground.

12. A method of level shifting an input logic signal IN with logic_—

0 (IN=0) and logic_—

1 (IN=1) states to a corresponding level shifted output logic signal that is one of OUT or OUT_X (corresponding to an inverted OUT), the method operable with a level shifter with a single voltage supply rail, comprising;

in response to the input logic signal IN,

providing OUT as an inverted IN at an OUT Node, including pulling up the OUT Node for OUT=1 (inverted IN=0), and pulling down the OUT Node for OUT=0 (inverted IN=1); and

providing IN_X as an inverted IN;

providing, based on OUT and IN_X, OUT_X as an inverted OUT at an OUT_X Node, including

providing pull-up/down for the OUT_X Node based on respectively IN_X=0 and IN_X=1;

controlling OUT_X Node pull-up/down based on an OUT control signal corresponding to OUT at the OUT Node;

such that, in response to IN_X and the OUT control signal, OUT_X is generated by;

for IN_X=0 and OUT=0, pulling up the OUT_X Node to generate OUT_X=1; and

for IN_X=1 and OUT=1, terminating OUT_X Node pull-up, and pulling down the OUT_X Node to OUT_X=0;

based on an OUT_X control signal corresponding to OUT_X, controlling an INT Node coupled between the OUT Node and the supply rail, including pulling up the INT Node based on OUT_X=0, and terminating INT Node pull-up based on OUT_X=1;

thereby controlling pull-up of the OUT and OUT_X Nodes based on respectively the OUT_X and OUT control signals, by;

for IN=0 (OUT=1, OUT_X=0), pulling down the OUT_X Node to OUT_X=0 in response to IN_X=1 and an OUT=1 control signal, and providing an OUT_X=0 control signal to control INT Node pull-up, and as a result pulling up the OUT Node to OUT=1; and

for IN=1 (OUT=0, OUT_X=1), pulling up the OUT_X Node to OUT_X=1 in response to IN_X=0 and an OUT=0 control signal, and providing an OUT_X=1 control signal to terminate INT Node pull up, and enable pulling down the OUT Node to OUT=0.

13. The method of claim 12, wherein providing OUT as an inverted IN at an OUT Node is accomplished by an IN inverter including PFET and NFET transistors, gate coupled at the IN Node, and drain-coupled at the OUT Node, the PFET source coupled to the INT Node and the NFET source coupled to the ground/reference.

14. The method of claim 12, wherein the INT Node is controlled by an INT_Node PFET transistor source coupled to the supply rail and drain coupled to the INT Node, and gate coupled to receive the OUT_X control signal.

15. The method of claim 14, wherein the INT_Node PFET connects the INT Node to the supply rail, such that, in response to an OUT_X=1 control signal, the INT Node is disconnected from the supply rail.

16. The method of claim 14, wherein providing OUT_X as an inverted OUT at an OUT_X Node is accomplished by an OUT_X network including:

an IN_X inverter configured to receive IN from the IN Node, and provide IN_X as an inverted IN at an IN_X Node; and

OUT_X circuitry including

OUT_X Node pull-up/down circuitry including pull-up PFET and pull-down NFET transistors, gate coupled to the IN_X Node, the pull-up PFET source coupled to the supply rail, and the pull-down NFET drain coupled to the OUT_X Node and source coupled to the ground/reference; and

an OUT_X Node PFET transistor series coupled between the pull-up PFET and the OUT_X Node, and gate coupled to the OUT Node to receive OUT as an OUT control signal;

the OUT_X circuitry configured to control OUT_X based on IN_X and the OUT control signal, such that;

for IN=0, the OUT_X circuitry receives IN_X=1 at the pull-up/down PFET and NFET, and an OUT=1 control signal at the OUT_X_Node PFET, pulling down the OUT_X Node to OUT_X=0, and providing an OUT_X=0 control signal to the INT_Node PFET, which pulls-up the INT Node and as a result the OUT Node is pulled up to OUT=1, and

for IN=1, the OUT_X circuitry receives IN_X=0 at the pull-up/down PFET and NFET, and an OUT=0 control signal at the OUT_X_Node PFET, pulling up the OUT_X Node to OUT_X=1, and providing an OUT_X=1 control signal to the INT_Node PFET, terminating pull-up of the INT Node.

17. The method of claim 16,

wherein the IN_X inverter includes PFET and NFET transistors, gate coupled to the IN Node, and drain-coupled at the IN_X Node, the PFET source coupled to the supply rail and the NFET source coupled to the ground/reference;

and

further comprising a diode connected PFET coupled between the supply rail and the PFET of the IN_X inverter, to reduce the supply voltage at the PFET source.

18. The method of claim 12, wherein the ground/reference comprises circuit ground.