Electronics device capable of efficient communication between components with asyncronous clocks

• US 9,225,343 B2
• Filed: 12/27/2011
• Issued: 12/29/2015
• Est. Priority Date: 08/17/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kothari, Love, Fullerton, Mark, Alarcon, Veronica, Rajan, Rajesh
• Primary Examiner(s): Guarino, Rahel
• Application Number:
  US13/338,001
• Publication Number:
  US 20130044844A1
• Time in Patent Office: 1,463 Days
• Field of Search: 375/360, 375/359, 375/370, 375/362, 375/372, 375/373, 327/41, 327/43, 327/141, 327/144, 327/145, 327/147, 711/400, 711/501, 711/500, 711/600
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/097 using a comparator for comparing the voltages obtained from two frequency to voltage converters
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.

Claims

1. An electronics apparatus, comprising:

a first electronics module configured to perform operations based on a first clock signal;

a second electronics module configured to perform operations based on a second clock signal, the second clock signal being slower than the first clock signal;

a latency reduction module configured to reduce latency during transfer of data between the first electronics module and the second electronics module that arises due to the difference between the first clock signal and the second clock signal, the latency reduction module including a buffer module configured to store the data; and

a controller module configured to generate the data, and to load the data into the buffer module using the first clock signal,

wherein the second electronics module is configured to retrieve data from the buffer module at a frequency of the second clock signal, and

wherein if a size of the data generated by the controller module exceeds a capacity of the buffer module, then the buffer module receives a portion of the data from the controller module, the portion of the data having a size substantially equal to the capacity of the buffer module.

2. The electronics apparatus of claim 1, wherein after the portion of the data has been received by the second electronics module from the buffer module, the buffer module generates an interrupt signal and forwards the interrupt signal to the controller module, and

after the controller module receives the interrupt signal, the buffer module receives a subsequent portion of the data.

3. The electronics apparatus of claim 1, wherein the latency reduction module includes a buffer bypass configured to transfer the data from the controller module to the second electronics module without the buffer module.

4. The electronics apparatus of claim 3, further comprising a multiplexer having an output connected to the second electronics module, the multiplexer being configured to select one of (1) an output of the buffer module or (2) the buffer bypass.

5. The electronics apparatus of claim 1, wherein the second electronics module includes a control portion configured to alter at least one of data and a setting within the second electronics module based on a command signal, and

the electronics apparatus further includes a command bus configured to supply the command signal from the controller module to the control portion.

6. The electronics apparatus of claim 1, wherein the controller module is further configured to retrieve the data from the second electronics module using the first clock signal.

7. The electronics apparatus of claim 6, wherein the controller module retrieves the data from the second electronics module a predetermined plurality of times.

8. The electronics apparatus of claim 7, wherein the controller module compares each of the predetermined plurality of data to each other, and

if the controller module determines that the each of the predetermined plurality of data is not substantially equal to one another. the controller module again retrieves the data from the second electronics module.

9. The electronics apparatus of claim 6, wherein the latency reduction module includes a clock monitoring module configured to monitor the second clock signal and to detect at least one of a rising edge and a falling edge of the second clock signal.

10. The electronics apparatus of claim 9, wherein the clock monitoring module only monitors the second clock signal while the controller module is retrieving the data.

11. The electronics apparatus of claim 10, wherein when the clock monitoring module detects the at least one of the rising edge and the falling edge of the second clock signal, the clock monitoring module generates an error signal and forwards the error signal to the controller module, and

upon receipt of the error signal, the controller module ignores the data retrieved.

12. The electronics apparatus of claim 10, wherein when the clock monitoring module detects the at least one of the rising edge and the falling edge of the second clock signal, the clock monitoring module generates an error signal and forwards the error signal to the controller module, and

upon receipt of the error signal, the controller module cancels a current data retrieval.

13. The electronics apparatus of claim 12, wherein upon receipt of the error signal, the controller module initiates a second data retrieval to again retrieve the data from the second electronics module.

14. The electronics apparatus of claim 11, wherein upon receipt of the error signal, the controller module initiates a second data retrieval to again retrieve the data from the second electronics module.

15. An electronics apparatus, comprising:

a first electronics module configured to perform operations based on a first clock signal;

a second electronics module configured to perform operations based on a second clock signal, the second clock signal being slower than the first clock signal;

a latency reduction module configured to reduce latency during transfer of data between the first electronics module and the second electronics module that arises due to the difference between the first clock signal and the second clock signal,

wherein the second electronics module includes a one-time programmable (OTP) module configured to store the data, and

the second electronics module includes an OTP power module configured to supply a write power, a read power, and no power to the OTP module.

16. The electronics apparatus of claim 15, wherein the first electronics module includes an OTP memory module configured to store the data,

the OTP power module supplies the read power to the OTP module,

the OTP memory module receives and stores the data from the OTP module, and

after the data has been stored in the OTP memory module, the OTP power module supplies no power to the OTP module.

17. The electronics apparatus of claim 16, further comprising a third electronics module configured to request the data from the first electronics module,

wherein the first electronics module supplies the data to the third electronics module from the OTP memory module.

18. A method of transferring data from a first electronics device operating at a first clock signal to a second electronics device operating at a second clock signal having a lower frequency than the first clock signal, the method comprising:

generating the data in the first electronics device;

loading the data in a buffer within the first electronics device using the first clock signal, the loading including loading a portion of the data into the buffer that is substantially equal in size to a capacity of the buffer when a size of the data exceeds the buffer capacity; and

retrieving, by the second electronics device, the plurality of data from the buffer at a frequency of the second clock signal.

19. A method of transferring data from a second electronics device operating at a second clock, signal to a first electronics device operating at a first clock signal having a higher frequency than the second clock signal, the method comprising:

retrieving the data, by the first electronics device, from the second electronics device using the first clock signal;

detecting whether the retrieving of the data by the first electronics device occurred during a rising edge or a falling edge of the second clock signal; and

if the retrieving of the data by the first electronics device occurred during the rising edge or the falling edge of the second clock signal, again retrieving the data, by the first electronics device, from the second electronics device using the first clock signal.