Electronics device capable of efficient communication between components with asyncronous clocks
First Claim
1. An electronics apparatus, comprising:
- a first electronics module configured to perform operations based on a first clock signal;
a second electronics module configured to perform operations based on a second clock signal, the second clock signal being slower than the first clock signal;
a latency reduction module configured to reduce latency during transfer of data between the first electronics module and the second electronics module that arises due to the difference between the first clock signal and the second clock signal, the latency reduction module including a buffer module configured to store the data; and
a controller module configured to generate the data, and to load the data into the buffer module using the first clock signal,wherein the second electronics module is configured to retrieve data from the buffer module at a frequency of the second clock signal, andwherein if a size of the data generated by the controller module exceeds a capacity of the buffer module, then the buffer module receives a portion of the data from the controller module, the portion of the data having a size substantially equal to the capacity of the buffer module.
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Abstract
An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.
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Citations
19 Claims
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1. An electronics apparatus, comprising:
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a first electronics module configured to perform operations based on a first clock signal; a second electronics module configured to perform operations based on a second clock signal, the second clock signal being slower than the first clock signal; a latency reduction module configured to reduce latency during transfer of data between the first electronics module and the second electronics module that arises due to the difference between the first clock signal and the second clock signal, the latency reduction module including a buffer module configured to store the data; and a controller module configured to generate the data, and to load the data into the buffer module using the first clock signal, wherein the second electronics module is configured to retrieve data from the buffer module at a frequency of the second clock signal, and wherein if a size of the data generated by the controller module exceeds a capacity of the buffer module, then the buffer module receives a portion of the data from the controller module, the portion of the data having a size substantially equal to the capacity of the buffer module. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An electronics apparatus, comprising:
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a first electronics module configured to perform operations based on a first clock signal; a second electronics module configured to perform operations based on a second clock signal, the second clock signal being slower than the first clock signal; a latency reduction module configured to reduce latency during transfer of data between the first electronics module and the second electronics module that arises due to the difference between the first clock signal and the second clock signal, wherein the second electronics module includes a one-time programmable (OTP) module configured to store the data, and the second electronics module includes an OTP power module configured to supply a write power, a read power, and no power to the OTP module. - View Dependent Claims (16, 17)
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18. A method of transferring data from a first electronics device operating at a first clock signal to a second electronics device operating at a second clock signal having a lower frequency than the first clock signal, the method comprising:
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generating the data in the first electronics device; loading the data in a buffer within the first electronics device using the first clock signal, the loading including loading a portion of the data into the buffer that is substantially equal in size to a capacity of the buffer when a size of the data exceeds the buffer capacity; and retrieving, by the second electronics device, the plurality of data from the buffer at a frequency of the second clock signal.
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19. A method of transferring data from a second electronics device operating at a second clock, signal to a first electronics device operating at a first clock signal having a higher frequency than the second clock signal, the method comprising:
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retrieving the data, by the first electronics device, from the second electronics device using the first clock signal; detecting whether the retrieving of the data by the first electronics device occurred during a rising edge or a falling edge of the second clock signal; and if the retrieving of the data by the first electronics device occurred during the rising edge or the falling edge of the second clock signal, again retrieving the data, by the first electronics device, from the second electronics device using the first clock signal.
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Specification