Method and system for controlling an interleaver
First Claim
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1. A controller for an interleaver, comprising:
- a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising;
receiving a first signal;
receiving a second signal; and
generating an interleaver control signal based on the first and second signals,wherein the first signal comprises a signal to noise ratio signal, andwherein the second signal is selected from a group consisting of a data rate signal and a bit error rate signal.
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Abstract
Systems and Methods for controlling an interleaver are disclosed. Generally, a first and second signal are received, wherein the first and second signals are selected from the group consisting of a signal to noise ration signal, a data rate signal, and a bit error rate signal. An interleaver control signal is then generated based on the first and second signals.
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Citations
19 Claims
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1. A controller for an interleaver, comprising:
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a processor; and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising; receiving a first signal; receiving a second signal; and generating an interleaver control signal based on the first and second signals, wherein the first signal comprises a signal to noise ratio signal, and wherein the second signal is selected from a group consisting of a data rate signal and a bit error rate signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for controlling an interleaver, the method comprising:
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receiving, by a system comprising a processor, a first signal; receiving, by the system, a second signal; and generating, by the system, an interleaver control signal based on the first and second signals, wherein the first signal comprises a signal to noise ratio signal, and wherein the second signal is selected from a group consisting of a data rate signal and a bit error rate signal. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification