Non-linear modeling of a physical system using look-up table with polynomial interpolation

• US 9,225,501 B2
• Filed: 03/31/2014
• Issued: 12/29/2015
• Est. Priority Date: 04/17/2013
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Azadet, Kameran
• Primary Examiner(s): Washburn, Daniel
• Assistant Examiner(s): Tadese, Berhanu
• Application Number:
  US14/230,622
• Publication Number:
  US 20140314181A1
• Time in Patent Office: 638 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/525 with means for reducing leakage of transmitter signal into the receiver
• CPC Class Codes: H04B 1/62 for providing a predistortion of the signal in the transmitter and corresponding correction in the receiver, e.g. for improving the signal/noise ratio
• CPC Class Codes: H04B 2001/0425 with linearisation using predistortion
• CPC Class Codes: H04B 7/0417 Feedback systems
• CPC Class Codes: H04J 11/004 using regenerative subtractive interference cancellation
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 25/03012 operating in the time domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/367 using predistortion
• CPC Class Codes: H04L 27/368 adaptive predistortion
• CPC Class Codes: H04L 5/1461 Suppression of signals in the return path, i.e. bidirectional control circuits

Abstract

Methods and apparatus are provided for non-linear modeling of a physical system using look-up tables with polynomial interpolation. A non-linear function is evaluated for a complex input value by obtaining at least one look-up table with polynomial interpolation that represents the non-linear function, wherein entries in the look-up table comprise polynomial coefficients of at least degree two for different segments of the non-linear function; obtaining a point from the look-up table that is near a magnitude of the complex input value; and generating a complex output value by evaluating the polynomial coefficients at the point to perform a Taylor Series expansion from said point. The non-linear function characterizes, for example, a power amplifier or an inverse of a power amplifier and the look-up tables can be used, for example, to implement digital pre-distortion.

Claims

1. A digital pre-distortion (DPD) system, comprising:

a digital signal processor configured to evaluate a non-linear function for a complex input value, comprising;

a memory configured to store at least one look-up table with polynomial interpolation that represents said non-linear function, wherein entries in said look-up table comprise polynomial coefficients of at least degree two for different segments of said non-linear function, said polynomial coefficients configured to provide at least one of a rectangular or triangular basis function for each segment of said non-linear function;

at least one processor, coupled to the memory, operative to;

obtain a point from said look-tip table that is near a magnitude of said complex input value; and

generate a complex output value by evaluating said polynomial coefficients at said point to perform a Taylor Series expansion from said point.

3. The method of claim 1, wherein said step of obtaining a point from said look-up table that is near said magnitude of said complex input value comprises obtaining two points that are near said magnitude of said complex input value and wherein said method further comprises the steps of evaluating said polynomial coefficients for said two points to perform a Taylor Series expansion from each point to form two intermediate values and linearly interpolating between said two intermediate values to generate said complex output value.

4. The method of claim 1, wherein said non-linear function characterizes one or more of a power amplifier and an inverse of a power amplifier.

5. The method of claim 1, wherein said one or more look-up tables are used to implement digital pre-distortion.

6. The method of claim 1, wherein said one or more look-up tables with polynomial interpolation are used in a processor instruction as part of an instruction set of one or more of a scalar processor and a vector processor.

7. The method of claim 6, wherein said look-up table is stored in a memory of said one or more of a scalar processor and a vector processor, and the polynomial interpolation is performed as part of a user-defined non-linear instruction that takes a complex number as an input, x, and computes ƒ

(x).

8. The method of claim 7, wherein said vector processor applies a complex input vector [x₁, x₂, . . . , x_N] to a plurality of non-linear functions f₁, f₂, . . . f_N to compute a complex vector output, f₁(x₁), f₂(x₂) . . . f_N(x_N).

9. The method of claim 1, wherein values in said look-up tables are obtained using one or more of a least squares algorithm, recursive least squares (RLS) and least mean square (LMS).

10. The method of claim 1, wherein said point that is near said magnitude of said complex input value comprises said point that is closest to said magnitude of said complex input value.

2. A digital pre-distortion (DPD) system, comprising:

a digital signal processor configured to evaluate a non-linear function for a complex input value, comprising;

a memory configured to store at least one look-up table with polynomial interpolation that represents said non-linear function, wherein entries in said look-up table comprise polynomial coefficients of at least degree two for different segments of said non-linear function;

at least one processor, coupled to the memory, operative to;

obtain a point from said look-tip table that is near a magnitude of said complex input value; and

generate a complex output value by evaluating said polynomial coefficients at said point to perform a Taylor Series expansion from said point,

wherein values in said look-up table are configured to be obtained using a direct optimization technique that obtains physical data for said non-linear function by applying a set of complex input samples x(n) to said non-linear function and measuring a complex output y(n) of said non-linear function and directly computes parameters φ

of a memory model for said non-linear function from said physical data, said memory model comprises one or more look-up tables having polynomial interpolation, and said parameters φ

produce a substantially minimum mean square error, said parameters φ

are provided for storage as entries in said one or more look-up tables.

11. A power amplifier, comprising:

a digital signal processor that evaluates a non-linear function for a complex input value, comprising;

a memory configured to store storing at least one look-up table with polynomial interpolation that represents said non-linear function, wherein entries in said look-up table comprise polynomial coefficients of at least degree two for different segments of said non-linear function, said polynomial coefficients configured to provide at least one of a rectangular or triangular basis function for each segment of said non-linear function; and

at least one processor, coupled to the memory, operative to;

obtain a point from said look-tip table that is near a magnitude of said complex input value; and

generate a complex output value by evaluating said polynomial coefficients at said point to perform a Taylor Series expansion from said point.

13. The digital signal processor of claim 11, wherein said step of obtaining a point from said look-up table that is near said magnitude of said complex input value comprises obtaining two points that are near said magnitude of said complex input value and wherein said digital signal processor further comprises the steps of evaluating said polynomial coefficients for said two points to perform a Taylor Series expansion from each point to form two intermediate values and linearly interpolating between said two intermediate values to generate said complex output value.

14. The digital signal processor of claim 11, wherein said non-linear function characterizes one or more of a power amplifier and an inverse of a power amplifier.

15. The digital signal processor of claim 11, wherein said one or more look-up tables are used to implement digital pre-distortion.

16. The digital signal processor of claim 11, wherein said one or more look-up tables with polynomial interpolation are used in a processor instruction as part of an instruction set of one or more of a scalar processor and a vector processor.

17. The digital signal processor of claim 11, wherein said digital signal processor is one or more of a scalar processor and a vector processor, and wherein the polynomial interpolation is performed as part of a user-defined non-linear instruction that takes a complex number as an input, x, and computes ƒ

(x).

18. The digital signal processor of claim 17, wherein said vector processor applies a complex input vector [x₁, x₂, . . . , x_N] to a plurality of non-linear functions f₁, f₂, . . . f_N to compute a complex vector output, f₁(x₁), f₂(x₂) . . . f_N(x_N).

19. The digital signal processor of claim 11, wherein values in said look-up tables are obtained using one or more of a least squares algorithm, recursive least squares (RLS) and least mean square (LMS).

20. The digital signal processor of claim 11, wherein said point that is near said magnitude of said complex input value comprises said point that is closest to said magnitude of said complex input value.

12. A power amplifier, comprising:

a digital signal processor that evaluates a non-linear function for a complex input value, comprising;

a memory configured to store at least one look-up table-with polynomial interpolation that represents said non-linear function, wherein entries in said look-up table comprise polynomial coefficients of at least degree two for different segments of said non-linear function; and

at least one processor, coupled to the memory, operative to;

obtain a point from said look-tip table that is near a magnitude of said complex input value; and

generate a complex output-value by evaluating said polynomial coefficients at said point to perform a Taylor Series expansion from said point,

wherein values in said look-up table are configured to be obtained using a direct optimization technique that obtains physical data for said non-linear function by applying a set of complex input samples x(n) to said non-linear function and measuring a complex output y(n) of said non-linear function and directly computes parameters φ

of a memory model for said non-linear function from said physical data, said memory model comprises one or more look-up tables having polynomial interpolation, and said parameters φ

produce a substantially minimum mean square error, said parameters φ

are provided for storage as entries in said one or more look-up tables.