System and method for synchronizing local oscillators

• US 9,225,507 B1
• Filed: 06/04/2013
• Issued: 12/29/2015
• Est. Priority Date: 06/04/2013
• Status: Active Grant

• Current Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Lye, William Michael, Cartina, Dragos
• Primary Examiner(s): Vlahos, Sophia
• Application Number:
  US13/910,016
• Time in Patent Office: 938 Days
• US Class Current: 1/1
• CPC Class Codes: G04F 10/00 Apparatus for measuring unknown time intervals by electric means
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H03L 7/235 Nested phase locked loops
• CPC Class Codes: H03M 1/00 Analogue/digital conversion; Digital/analogue conversion conversion of analogue values to or from differential modulation H03M3/00
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/1255 Synchronisation of the sampling frequency or phase to the input frequency or phase
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.

Claims

1. An apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path, the apparatus comprising:

a synchronization channel utilizing at least one of transmit buffers and receive buffers, the synchronization channel configured to exchange a synchronization clock between the first and second RF paths;

a first phase detector configured to measure a phase alignment between the first and second LO clocks and to generate an output;

a second phase detector configured to measure the phase alignment between the second and first LO clocks and to generate an output; and

a loop filter configured to drive the controllable LO clock generator using the phase alignments,

wherein;

the first RF path includes the first phase detector,

the second RF path includes the second phase detector,

the outputs from the first and second phase detectors are subtracted at the input of the loop filter,

a true phase relationship between the first and second LO clocks is determined, and

systematic and environmental variability due to the at least one of transmit buffers and receive buffers is cancelled.

2. The apparatus of claim 1 wherein the RF paths comprise a low-bandwidth phase locked loop and wherein the loop filter is further configured to manipulate a phase of the low-bandwidth phase locked loop to align the first and second LO clocks.

3. The apparatus of claim 1, further comprising:

a first printed circuit board (PCB) trace or connector configured to pass a first full rate clock from the first RF path to the second RF path; and

a second PCB trace or connector configured to pass a second full rate clock from the second RF path to the first RF path;

wherein the first and second phase detectors are configured to measure a relative phase of the first and second full rate clocks.

4. The apparatus of claim 2, further comprising:

a first PCB trace or connector configured to pass a first low rate clock from the first RF path to the second RF path; and

a second PCB trace or connector configured to pass a second low rate clock from the second RF path to the first RF path;

wherein the first and second phase detectors are configured to measure a relative phase of the first and second low rate clocks.

5. The apparatus of claim 4, wherein the first and second low rate clocks are synchronously generated and aligned to first and second full rate clocks.

6. The apparatus of claim 1, further comprising:

a PCB trace or connector configured to pass, in a time interleaved manner, first and second full rate clocks of the first and second RF paths between the first and second RF paths; and

wherein the first phase detector is configured to measure a relative phase of the first and second full rate clocks when the PCB trace or connector is passing the second full rate clock from the second RF path; and

wherein the second phase detector is configured to measure the relative phase of the first and second full rate clocks when the PCB trace or connector is passing the first full rate clock from the first RF path.

7. The apparatus of claim 1, further comprising:

a PCB trace or connector configured to pass, in a time interleaved manner, first and second low rate clocks of the first and second RF paths between the first and second RF paths; and

wherein the first phase detector is configured to measure a relative phase of the first and second low-rate clocks when the PCB trace or connector is passing the second low rate clock from the second RF path; and

wherein the second phase detector is configured to measure the relative phase of the first and second low-rate clocks when the PCB trace or connector is passing the first low rate clock from the first RF path.

8. The apparatus of claim 7, wherein the first and second low rate clocks are synchronously generated and aligned to first and second full rate clocks.

9. The apparatus of claim 1, wherein the output from the first phase detector and the output from the second phase detector are determined from three time-interleaved measurements, and the apparatus further comprises:

at least one replica receive buffer configured to cancel systematic and environmental variability due to the at least one of the transmit buffers and the receive buffers.

10. The apparatus of claim 1, wherein the apparatus for aligning first and second local oscillator clocks includes separate time-interleaved operations.

11. The apparatus of claim 10, wherein any one of the time interleaving, communication between the first phase detector and the loop filter, communication between the second phase detector and the loop filter, and the loop filter is implemented with software.

12. The apparatus of claim 1, further comprising:

an embedded channel in the clock synchronization channel configured to communicate the first phase detector output and the second phase detector output between the first and second RF paths.

13. The apparatus of claim 1, further comprising:

a network of clock synchronization ports configured to align a plurality of LO clocks in a plurality of RF paths through distributed phase detection.

14. The apparatus of claim 13, wherein the network of clock synchronization ports is constructed using any one or more of daisy chain, ring, hypercube, star, or fully-connected topologies.

15. A method for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path, the method comprising:

exchanging synchronization clocks between the first and second RF paths over a synchronization channel, the synchronization channel utilizing at least one of transmit buffers and receive buffers;

measuring a phase alignment between the first and second LO clocks with a first phase detector and a second phase detector, the first phase detector being included in the first RF path, the second phase detector being included in the second RF path, the measuring of the phase alignment comprising;

subtracting an output from each of the first phase detector and the second phase detector at the input of a loop filter;

determining a true phase relationship between the LO clocks; and

cancelling systematic and environmental variability due to the at least one of transmit buffers and receive buffers;

and

driving, with the loop filter, the controllable LO clock generator using the phase alignment.

16. The method of claim 15 wherein the first and second RF paths comprise a low-bandwidth phase locked loop and wherein the method further comprises:

manipulating a phase of the low-bandwidth phase locked loop to align the first and second LO clocks.

17. The method of claim 15, further comprising:

passing a first full rate clock from the first RF path to the second RF path over a first printed circuit board (PCB) trace or connector;

passing a second full rate clock from the second RF path to the first RF path over a second PCB trace or connector; and

wherein measuring the phase alignment between the first and second LO clocks comprises measuring a relative phase of the first and second full rate clocks.

18. The method of claim 15, further comprising:

passing a first low rate clock from the first RF path to the second RF path over a first PCB trace or connector;

passing a second low rate clock from the second RF path to the first RF path over a second PCB trace or connector; and

wherein measuring the phase alignment between the first and second LO clocks comprises measuring a relative phase of the first and second low rate clocks.

19. The method of claim 18 wherein the first and second low rate clocks are synchronously generated and aligned to first and second full rate clocks.

20. The method of claim 15, further comprising:

passing, in a time interleaved manner, first and second full rate clocks of the first and second RF paths between the first and second RF paths over a PCB trace or connector; and

wherein measuring the phase alignment between the first and second LO clocks comprises measuring a relative phase of the first and second full rate clocks.

21. The method of claim 15, further comprising:

passing, in a time interleaved manner, first and second low rate clocks of the first and second RF paths between the first and second RF paths over a PCB trace or connector; and

wherein measuring the phase alignment between the first and second LO clocks comprises measuring a relative phase of the first and second low rate clocks.

22. The method of claim 21, wherein the first and second low rate clocks are synchronously generated and aligned to first and second full rate clocks.

23. The method of claim 15, further comprising:

determining the output of the first phase detector and the output of the second phase detector from three time-interleaved measurements, wherein cancelling systematic and environmental variability due to the at least one of transmit buffers and receive buffers is effected using at least one of a replica receive buffer and a replica transmit buffer.

24. The method of claim 15, wherein the method for aligning the first and second local oscillator clocks includes separate time-interleaved operations.

25. The method of claim 24, wherein any one of the time interleaving, communication between the first phase detector and the loop filter, communication between the second phase detector and the loop filter, and the loop filter is implemented with software.

26. The method of claim 15, further comprising:

implementing communication of the first phase detector output and the second phase detector output between the first and second RF paths by embedding a channel in the clock synchronization channel.

27. The method of claim 15, further comprising:

aligning a plurality of LO clocks in a plurality of separate RF paths through distributed phase detection over a network of clock synchronization ports.

28. The method of claim 27, wherein the network of clock synchronization ports is constructed using any one or more of daisy chain, ring, hypercube, star, or fully-connected topologies.