Data rate programming using source degenerated CTLE

• US 9,225,560 B1
• Filed: 04/08/2015
• Issued: 12/29/2015
• Est. Priority Date: 04/08/2015
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Inphi Corporation
• Inventors: Mishra, Parmanand, Harwood, Michael S.
• Primary Examiner(s): Wang, Ted
• Application Number:
  US14/681,989
• Time in Patent Office: 265 Days
• US Class Current: 1/1
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H04B 10/58 Compensation for non-linear transmitter output
• CPC Class Codes: H04B 10/6163 Compensation of non-linear effects in the fiber optic link, e.g. self-phase modulation [SPM], cross-phase modulation [XPM], four wave mixing [FWM]
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

The present invention is directed to data communication systems and methods. In various embodiments, the present invention provides a CML device that changes output frequency response by varying resistance values of its load resistance and source resistance. A bias control voltage is used to adjust the tail current of the CML device, and the tail current adjusts the output gain of the CML device. There are other embodiments as well.

Claims

1. A continuous time linear equalizer device comprising:

a first input and a second input for receiving data;

a first transistor comprising a first gate and a first output terminal and a first source terminal, the first gate being electrically coupled to the first input;

a second transistor comprising a second gate and a second output terminal and a second source terminal, the second gate being electrically coupled to the second input;

a first resistor module comprising a first plurality of resistors, the first resistor module being coupled to the first output terminal, the first resistor module being characterized by a first variable resistance value;

a second resistor module comprising a second plurality of resistors, the second resistor module being coupled to the second output terminal, the second resistor module being characterized by a second variable resistance value, the second variable resistance value being substantially equal to the first variable resistance value;

a third resistor module comprising a third plurality of resistors, the third resistor module being coupled to the first source terminal and the second source terminal, the third resistor module being characterized by a third variable resistance value;

a third transistor module comprising a third gate and a first drain terminal, the first drain terminal being electrically coupled to the first source terminal; and

a comparator being configured to generate a bias voltage based on at least a common output voltage and a reference voltage, the bias voltage being electrical coupled to the third gate.

2. The device of claim 1 wherein the first plurality of resistors are configured in parallel.

3. The device of claim 1 further comprising a fourth transistor module comprising a fourth gate and a second drain terminal, the second drain terminal being electrically coupled to the second source terminal.

4. The device of claim 1 wherein the first drain terminal is electrically coupled to third resistor module.

5. The device of claim 1 further comprising a capacitor configured in parallel to the third resistor module.

6. The device of claim 1 further comprising a first resistor and a second resistor, the common output voltage being coupled to the first output terminal via the first resistor and coupled to the second output terminal via the second resistor.

7. The device of claim 1 wherein the first resistance value corresponds to a predetermined data rate.

8. The device of claim 1 wherein a ratio between the first resistance value and the third resistance value corresponds to a predetermined output gain level.

9. The device of claim 1 wherein the third resistance value corresponds to a zero frequency of an output voltage.

10. The device of claim 1 wherein the first resistor module comprises a DAC for selecting the first plurality of resistors.

11. A communication system comprising:

a first communication line and a second communication line;

a control module;

a CTLE coupled to the first communication line and the second communication line, wherein the CTLE comprises;

a first input and a second input for receiving data;

a first transistor comprising a first gate and a first output terminal and a first source terminal, the first gate being electrically coupled to the first input;

a second transistor comprising a second gate and a second output terminal and a second source terminal, the second gate being electrically coupled to the second input;

a first resistor module comprising a first plurality of resistors, the first resistor module being coupled to the first output terminal, the first resistor module being characterized by a first variable resistance value, the first variable resistance value being adjustable in response to control signals from the control module;

a second resistor module comprising a second plurality of resistors, the second resistor module being coupled to the second output terminal, the second resistor module being characterized by a second variable resistance value, the second variable resistance value being substantially equal to the first variable resistance value;

a third resistor module comprising a third plurality of resistors, the third resistor module being coupled to the first source terminal and the second source terminal, the third resistor module being characterized by a third variable resistance value;

a third transistor module comprising a third gate and a first drain terminal, the first drain terminal being electrically coupled to the first source terminal; and

a comparator being configured to generate a bias voltage based on at least a common output voltage and a reference voltage, the bias voltage being electrical coupled to the third gate.

12. The system of claim 11 wherein the control module is configured to generate the control signals based on a predetermined data rates.

13. The system of claim 11 wherein the third plurality of resistors are configured in parallel.

14. The system of claim 11 wherein the first communication line comprises an optical communication line.

15. The system of claim 11 further comprising a SerDes module coupled to the first output terminal and the second output terminal.

16. A continuous time linear equalizer device comprising:

a first input and a second input for receiving data;

a first transistor comprising a first gate and a first output terminal and a first source terminal, the first gate being electrically coupled to the first input;

a second transistor comprising a second gate and a second output terminal and a second source terminal, the second gate being electrically coupled to the second input;

a first resistor module comprising a first plurality of resistors, the first resistor module being coupled to the first output terminal, the first resistor module being characterized by a first variable resistance value;

a second resistor module comprising a second plurality of resistors, the second resistor module being coupled to the second output terminal, the second resistor module being characterized by a second variable resistance value, the second variable resistance value being substantially equal to the first variable resistance value;

a third resistor module comprising a third plurality of resistors, the third resistor module being coupled to the first source terminal and the second source terminal, the third resistor module being characterized by a third variable resistance value;

a third transistor module comprising a third gate and a first drain terminal, the first drain terminal being electrically coupled to the first source terminal; and

a comparator being configured to generate a bias voltage based on a control signal;

wherein the control is provided by a current DAC module.

17. The device of claim 16 further comprising a control module for generating the control signal.

18. The device of claim 16 further comprising a capacitor electrically coupled to the first resistor module.

19. The device of claim 16 wherein the bias voltage is coupled to the third gate.