Data rate programming using source degenerated CTLE
First Claim
Patent Images
1. A continuous time linear equalizer device comprising:
- a first input and a second input for receiving data;
a first transistor comprising a first gate and a first output terminal and a first source terminal, the first gate being electrically coupled to the first input;
a second transistor comprising a second gate and a second output terminal and a second source terminal, the second gate being electrically coupled to the second input;
a first resistor module comprising a first plurality of resistors, the first resistor module being coupled to the first output terminal, the first resistor module being characterized by a first variable resistance value;
a second resistor module comprising a second plurality of resistors, the second resistor module being coupled to the second output terminal, the second resistor module being characterized by a second variable resistance value, the second variable resistance value being substantially equal to the first variable resistance value;
a third resistor module comprising a third plurality of resistors, the third resistor module being coupled to the first source terminal and the second source terminal, the third resistor module being characterized by a third variable resistance value;
a third transistor module comprising a third gate and a first drain terminal, the first drain terminal being electrically coupled to the first source terminal; and
a comparator being configured to generate a bias voltage based on at least a common output voltage and a reference voltage, the bias voltage being electrical coupled to the third gate.
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Abstract
The present invention is directed to data communication systems and methods. In various embodiments, the present invention provides a CML device that changes output frequency response by varying resistance values of its load resistance and source resistance. A bias control voltage is used to adjust the tail current of the CML device, and the tail current adjusts the output gain of the CML device. There are other embodiments as well.
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Citations
19 Claims
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1. A continuous time linear equalizer device comprising:
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a first input and a second input for receiving data; a first transistor comprising a first gate and a first output terminal and a first source terminal, the first gate being electrically coupled to the first input; a second transistor comprising a second gate and a second output terminal and a second source terminal, the second gate being electrically coupled to the second input; a first resistor module comprising a first plurality of resistors, the first resistor module being coupled to the first output terminal, the first resistor module being characterized by a first variable resistance value; a second resistor module comprising a second plurality of resistors, the second resistor module being coupled to the second output terminal, the second resistor module being characterized by a second variable resistance value, the second variable resistance value being substantially equal to the first variable resistance value; a third resistor module comprising a third plurality of resistors, the third resistor module being coupled to the first source terminal and the second source terminal, the third resistor module being characterized by a third variable resistance value; a third transistor module comprising a third gate and a first drain terminal, the first drain terminal being electrically coupled to the first source terminal; and a comparator being configured to generate a bias voltage based on at least a common output voltage and a reference voltage, the bias voltage being electrical coupled to the third gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A communication system comprising:
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a first communication line and a second communication line; a control module; a CTLE coupled to the first communication line and the second communication line, wherein the CTLE comprises; a first input and a second input for receiving data; a first transistor comprising a first gate and a first output terminal and a first source terminal, the first gate being electrically coupled to the first input; a second transistor comprising a second gate and a second output terminal and a second source terminal, the second gate being electrically coupled to the second input; a first resistor module comprising a first plurality of resistors, the first resistor module being coupled to the first output terminal, the first resistor module being characterized by a first variable resistance value, the first variable resistance value being adjustable in response to control signals from the control module; a second resistor module comprising a second plurality of resistors, the second resistor module being coupled to the second output terminal, the second resistor module being characterized by a second variable resistance value, the second variable resistance value being substantially equal to the first variable resistance value; a third resistor module comprising a third plurality of resistors, the third resistor module being coupled to the first source terminal and the second source terminal, the third resistor module being characterized by a third variable resistance value; a third transistor module comprising a third gate and a first drain terminal, the first drain terminal being electrically coupled to the first source terminal; and a comparator being configured to generate a bias voltage based on at least a common output voltage and a reference voltage, the bias voltage being electrical coupled to the third gate. - View Dependent Claims (12, 13, 14, 15)
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16. A continuous time linear equalizer device comprising:
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a first input and a second input for receiving data; a first transistor comprising a first gate and a first output terminal and a first source terminal, the first gate being electrically coupled to the first input; a second transistor comprising a second gate and a second output terminal and a second source terminal, the second gate being electrically coupled to the second input; a first resistor module comprising a first plurality of resistors, the first resistor module being coupled to the first output terminal, the first resistor module being characterized by a first variable resistance value; a second resistor module comprising a second plurality of resistors, the second resistor module being coupled to the second output terminal, the second resistor module being characterized by a second variable resistance value, the second variable resistance value being substantially equal to the first variable resistance value; a third resistor module comprising a third plurality of resistors, the third resistor module being coupled to the first source terminal and the second source terminal, the third resistor module being characterized by a third variable resistance value; a third transistor module comprising a third gate and a first drain terminal, the first drain terminal being electrically coupled to the first source terminal; and a comparator being configured to generate a bias voltage based on a control signal;
wherein the control is provided by a current DAC module. - View Dependent Claims (17, 18, 19)
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Specification