Power semiconductor module

• US 9,226,430 B2
• Filed: 03/07/2013
• Issued: 12/29/2015
• Est. Priority Date: 12/27/2012
• Status: Expired due to Fees

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Kim, Kwang Soo, Kim, Tae Hyun, Suh, Bum Seok, Jeong, In Wha, Lee, Young Ki
• Primary Examiner(s): Smith, Courtney
• Application Number:
  US13/789,030
• Publication Number:
  US 20140185242A1
• Time in Patent Office: 1,027 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48229 the bond pad protruding from the surface of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15159 Side view
• CPC Class Codes: H05K 7/209 Heat transfer by conduction from internal heat source to heat radiating structure H05K7/20909 takes precedence

Abstract

There is provided a power semiconductor module in which power semiconductor elements, integration of which may be difficult due to heating, are modularized. The power semiconductor module includes: a heat dissipation substrate electrically connected to a common connection terminal; and a plurality of electronic elements disposed on the heat dissipation substrate, wherein the electronic elements have varying spaces therebetween.

Claims

1. A power semiconductor module comprising:

a common connection terminal that is a collector terminal;

external connection terminals, including a gate connection terminal and an emitter connection terminal;

a heat dissipation substrate electrically connected to the common connection terminal; and

a plurality of electronic elements disposed on the heat dissipation substrate, the electronic elements having varying spaces therebetween and being disposed such that spaces therebetween are increased in width in a direction closer to the common connection terminal.

2. The power semiconductor module of claim 1, further comprising:

a base substrate;

at least one circuit board disposed on the base substrate,

wherein the heat dissipation substrate is disposed on the circuit board and the electronic elements are electrically connected to the common connection terminal through the heat dissipation substrate and the circuit board.

3. The power semiconductor module of claim 2, wherein the circuit board comprises a first circuit board to which the gate connection terminal is attached, a second circuit board to which the emitter connection terminal is attached, and a third circuit board to which the common connection terminal is attached.

4. The power semiconductor module of claim 3, wherein the electronic elements are electrically connected to the first and third circuit boards through bonding wires.

5. The power semiconductor module of claim 2, further comprising:

a support substrate disposed below the base substrate and dissipating heat transmitted from the base substrate outwardly.

6. A power semiconductor module comprising:

a heat dissipation substrate electrically connected to a common connection terminal; and

a plurality of electronic elements disposed on the heat dissipation substrate, the plurality of electronic elements having varying spaces therebetween,

wherein the electronic elements are classified as first, second, third, and fourth electronic elements according to an order in which the electronic elements are disposed to be adjacent to the common connection terminal, and intervals X₁, X₂, and X₃ between the electronic elements satisfy Equation 1 shown below;

0.8d>

X₁+X₂+X₃>

0.4d 

 

[Equation 1]

wherein d is an overall length of the heat dissipation substrate 50, X₁ is a space between the first electronic element and the second electronic element, X₂ is a space between the second electronic element and the third electronic element, and X₃ is a space between the third electronic element and the fourth electronic element.

7. The power semiconductor module of claim 6, wherein X₁, X₂, and X₃ satisfy Equation 2 shown below:

X₁>

X₂>

X₃. 

 

[Equation 2]

8. The power semiconductor module of claim 6, wherein X₃ and X₂ satisfy Equation 3 and Equation 4 shown below:

X₃=(1.5˜

3)X₂=(1.5˜

15)X₁ 

 

[Equation 3]

X₂=(1.0˜

5)X₁. 

 

[Equation 4]

9. A power semiconductor module comprising:

a heat dissipation substrate electrically connected to a common connection terminal; and

a plurality of electronic elements disposed on the heat dissipation substrate, the plurality of electronic elements having varying spaces therebetween,

the heat dissipation substrate having different thicknesses according to positions of the electronic elements.

10. The power semiconductor module of claim 9, wherein the heat dissipation substrate has reduced thicknesses in a direction away from the common connection terminal.

11. The power semiconductor module of claim 10, wherein the heat dissipation substrate has steps formed according to positions of the electronic elements.

12. The power semiconductor module of claim 11, wherein the electronic elements are classified as first, second, third, and fourth electronic elements according to an order in which the electronic elements are disposed to be adjacent to the common connection terminal, and intervals X′

₁, X′

₂, and X′

₃ between the electronic elements satisfy Equation 5 through Equation 7 shown below;

H₄=(X′

₄/X′

₃)H₃ 

 

[Equation 5]

H₃=(X′

₃/X′

₂)H₂ 

 

[Equation 6]

H₂=(X′

₂/X′

₁)H₁ 

 

[Equation 7]

wherein H₄ is a height of the heat dissipation substrate at which the first electronic element is disposed, H₃ is a height of the heat dissipation substrate at which the second electronic element is disposed, H₂ is a height of the heat dissipation substrate at which the third electronic element is disposed, H₁ is a height of the heat dissipation substrate at which the fourth electronic element is disposed, X′

₄ is a distance of the mounting surface of the heat dissipation substrate at which the first electronic device is disposed, X′

₃ is a distance of the mounting surface of the heat dissipation substrate at which the second electronic device is disposed, X′

₂ is a distance of a mounting surface of the heat dissipation substrate at which the third electronic element is disposed, and X′

₁ is a distance of a mounting surface of the heat dissipation substrate at which the fourth electronic element is disposed.

13. A power semiconductor module comprising:

a common connection terminal that is a collector terminal;

a plurality of external connection terminals, including a gate terminal and an emitter terminal; and

a plurality of power semiconductor packages disposed in a row from the common connection terminal and electrically connected to the common connection terminal, the power semiconductor packages being disposed such that spaces therebetween are reduced in a direction away from the common connection terminal.