Methods and apparatus for debugging lowest power states in System-On-Chips
First Claim
1. A method for debugging a finite state machine (FSM) that sequences System-On-Chips (SOCs) through low power states including a lowest power state, comprising:
- implementing an on-chip debug logic circuit;
connecting the debug logic circuit to a power gate-able voltage source of a system on chip (SoC);
operating the finite state machine connected to an Always On voltage source to sequence the SoC through the low power states by moving from a low power state to a next low power state and generating respective output signals corresponding to the low power states;
masking the respective output signals to generate respective masked output signals;
applying the respective masked output signals to circuit elements of the SoC to prevent the debug logic circuit from transitioning into the low power states;
applying the respective masked output signals to circuit elements of the debug logic circuit to prevent the debug logic circuit from entering into a reset state;
anddebugging the finite state machine in the lowest power state by the debug logic circuit.
1 Assignment
0 Petitions
Accused Products
Abstract
Methods and apparatus for debugging finite state machine are disclosed. The method includes implementing a debug logic circuit and connecting the debug logic circuit to a system on chip (SoC) voltage source. The method includes operating a finite state machine that sequences the SoC from a low power state to a next low power state and generating respective output signals corresponding to the low power states and wherein the finite state machine is connected to Always On voltage source. The method includes masking the output signals to generate respective masked output signals, and applying the masked output signals to SoC circuit elements to prevent from transitioning into low power states and hence keeping the debug logic circuitry alive. The method includes debugging the finite state machine in the lowest power state by the debug logic circuit.
-
Citations
24 Claims
-
1. A method for debugging a finite state machine (FSM) that sequences System-On-Chips (SOCs) through low power states including a lowest power state, comprising:
-
implementing an on-chip debug logic circuit; connecting the debug logic circuit to a power gate-able voltage source of a system on chip (SoC); operating the finite state machine connected to an Always On voltage source to sequence the SoC through the low power states by moving from a low power state to a next low power state and generating respective output signals corresponding to the low power states; masking the respective output signals to generate respective masked output signals; applying the respective masked output signals to circuit elements of the SoC to prevent the debug logic circuit from transitioning into the low power states; applying the respective masked output signals to circuit elements of the debug logic circuit to prevent the debug logic circuit from entering into a reset state; and debugging the finite state machine in the lowest power state by the debug logic circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. An integrated circuit, comprising:
-
a finite state machine configured to sequence a system on chip (SoC) through low power states including a lowest power state and generating respective output signals corresponding to the low power states; a debug logic circuit connected to the finite state machine and configured to debug the finite state machine; a system on chip (SoC) voltage source connected to the debug logic circuit; a masking circuit configured to mask the output signals and to generate masked output signals, wherein the masked output signals are applied to circuit elements of the SoC to prevent the SoC circuit elements from transitioning into the low power states and to prevent the debug logic circuit from entering into reset, and wherein the debug logic circuit debugs the finite state machine as the finite state machine sequences the SoC through the lowest power state. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
-
Specification