Methods and apparatus for debugging lowest power states in System-On-Chips

• US 9,229,053 B2
• Filed: 01/28/2014
• Issued: 01/05/2016
• Est. Priority Date: 01/28/2014
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Ng, Kwanjee, Krishnani, Padam, Agrawal, Supreet
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US14/165,871
• Publication Number:
  US 20150212154A1
• Time in Patent Office: 707 Days
• Field of Search: 714/745, 713/320, 713/323
• US Class Current: 1/1
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/329 by task scheduling

Abstract

Methods and apparatus for debugging finite state machine are disclosed. The method includes implementing a debug logic circuit and connecting the debug logic circuit to a system on chip (SoC) voltage source. The method includes operating a finite state machine that sequences the SoC from a low power state to a next low power state and generating respective output signals corresponding to the low power states and wherein the finite state machine is connected to Always On voltage source. The method includes masking the output signals to generate respective masked output signals, and applying the masked output signals to SoC circuit elements to prevent from transitioning into low power states and hence keeping the debug logic circuitry alive. The method includes debugging the finite state machine in the lowest power state by the debug logic circuit.

Claims

1. A method for debugging a finite state machine (FSM) that sequences System-On-Chips (SOCs) through low power states including a lowest power state, comprising:

implementing an on-chip debug logic circuit;

connecting the debug logic circuit to a power gate-able voltage source of a system on chip (SoC);

operating the finite state machine connected to an Always On voltage source to sequence the SoC through the low power states by moving from a low power state to a next low power state and generating respective output signals corresponding to the low power states;

masking the respective output signals to generate respective masked output signals;

applying the respective masked output signals to circuit elements of the SoC to prevent the debug logic circuit from transitioning into the low power states;

applying the respective masked output signals to circuit elements of the debug logic circuit to prevent the debug logic circuit from entering into a reset state;

and

debugging the finite state machine in the lowest power state by the debug logic circuit.

2. The method of claim 1, wherein the respective masked output signals prevent IOs of the SoC from transitioning to the low power states.

3. The method of claim 1, wherein the respective masked output signals override isolation cells.

4. The method of claim 1, wherein the respective masked output signals prevent a voltage rail of the SoC from turning off.

5. The method of claim 1, wherein the respective masked output signals override debug reset signals.

6. The method of claim 1, further comprising:

applying a first input signal to the finite state machine;

transitioning the finite state machine from an idle state to an isolation state in response to the first input signal;

generating and asserting by the finite state machine a first output signal during the transitioning into the isolation state;

masking the first output signal to generate a first masked output signal; and

applying the first masked output signal to IOs of the SoC.

7. The method of claim 6, further comprising:

transitioning the finite state machine from the isolation state to a power down state;

generating and asserting by the finite state machine a second output signal during the transitioning to the power down state;

masking the second output signal to generate a second masked output signal; and

applying the second masked output signal to isolation cells.

8. The method of claim 7, further comprising:

transitioning by the finite state machine from the power down state to a wake state; and

generating and asserting a third output signal during the transitioning into the wake state, wherein the third output signal prevents a power rail of the SoC from turning off.

9. The method of claim 8, further comprising:

transitioning by the finite state machine from the wake state to a leave power down state; and

de-asserting the third output signal during the transitioning into the leave power down state.

10. The method of claim 9, further comprising:

transitioning by the finite state machine from the leave power down state to a remove isolation state; and

de-asserting the first output signal during the transitioning to the remove isolation state.

11. The method of claim 10, further comprising:

transitioning by the finite state machine from the remove isolation state to the idle state;

de-asserting the second output signal during the transitioning to the idle state; and

generating and asserting by the finite state machine a fourth output signal during the transitioning to the idle state;

masking the fourth output signal to generate a fourth masked output signal;

applying the fourth masked output signal to the debug logic circuit preventing it from entering into reset;

generating and asserting by the finite state machine a fifth output signal during the transitioning to the idle state;

applying the fifth output signal directly without masking to the SoC circuit elements to enter into reset.

12. An integrated circuit, comprising:

a finite state machine configured to sequence a system on chip (SoC) through low power states including a lowest power state and generating respective output signals corresponding to the low power states;

a debug logic circuit connected to the finite state machine and configured to debug the finite state machine;

a system on chip (SoC) voltage source connected to the debug logic circuit;

a masking circuit configured to mask the output signals and to generate masked output signals,

wherein the masked output signals are applied to circuit elements of the SoC to prevent the SoC circuit elements from transitioning into the low power states and to prevent the debug logic circuit from entering into reset, and wherein the debug logic circuit debugs the finite state machine as the finite state machine sequences the SoC through the lowest power state.

13. The integrated circuit of claim 12, wherein the masked output signals prevent IOs of the SoC from transitioning to the low power states.

14. The integrated circuit of claim 12, wherein the masked output signals override IOs of the SoC from powering down.

15. The integrated circuit of claim 12, wherein the masked output signals override isolation cells.

16. The integrated circuit of claim 12, wherein the masked output signals allow IOs of the SoC to remain powered-up for use by the debug logic circuitry.

17. The integrated circuit of claim 12, wherein the masked output signals prevent a voltage rail of the SoC from turning off.

18. The integrated circuit of claim 12, wherein the masked output signals override a debug reset signal.

19. The integrated circuit of claim 12, further comprising:

a flip-flop circuit and a 2×

1 mux configured to receive a first output signal from the finite state machine when the finite state machine transitions from an idle state to an isolation state in response to a first input signal, the masking circuit configured to generate a first masked output signal, wherein the first masked output signal is applied to IOs of the SoC.

20. The integrated circuit of claim 19, wherein the flip-flop circuit and a second 2×

1 mux are configured to receive a second output signal from the finite state machine when the finite state machine transitions from the isolation state to a power down state, wherein the masking circuit is configured to generate a second masked output signal, and wherein the second masked output signal is applied to isolation cells.

21. The integrated circuit of claim 20, wherein the flip-flop circuit and a third 2×

1 mux are configured to receive a third output signal from the finite state machine when the finite state machine transitions from the power down state to a wake state, wherein the masking circuit is configured to generate a third masked output signal, and wherein the third masked output signal prevents a power rail of the SoC from turning off.

22. The integrated circuit of claim 21, wherein the finite state machine is configured to transition from the wake state to a leave power down state, and wherein the finite state machine de-asserts the third output signal in the leave power down state.

23. The integrated circuit of claim 22, wherein the finite state machine is configured to transition from the leave power down state to a remove isolation state and is configured to de-assert the first output signal.

24. The integrated circuit of claim 23, wherein the flip-flop circuit and a fourth 2×

1 mux are configured to receive a fourth output signal from the finite state machine when the finite state machine transitions from the remove isolation state to the idle state, wherein the masking circuit is configured to generate the fourth masked output signal, and wherein the fourth masked output signal prevents the debug logic circuit from entering into reset.