Decompressed scan chain masking circuit shift register with log2(n/n) cells

• US 9,229,055 B2
• Filed: 06/18/2015
• Issued: 01/05/2016
• Est. Priority Date: 06/11/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Narayanan, Prakash, Jain, Arvind, Subramanian, Sundarrajan, Parekhji, Rubin A.
• Primary Examiner(s): Bonzo, Bryce
• Assistant Examiner(s): Mehrmanesh, Elmira
• Application Number:
  US14/743,720
• Publication Number:
  US 20150285860A1
• Time in Patent Office: 201 Days
• Field of Search: 714725-731, 714/738
• US Class Current: 1/1
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Claims

1. Electronic scan circuitry comprising:

a decompressor;

a plurality of scan chains fed by the decompressor;

a masking circuit fed by the plurality of scan chains, the scan chains scannable to scan them out in scan out cycles through the masking circuit; and

a scannable masking qualification circuit coupled to the masking circuit and operable both to select at least one of the plurality of scan chains for disqualification and to execute the disqualification on a selected scan out cycle,

the scannable masking qualification circuit including a scan-programmable shift register fed by the decompressor and accommodating at least a number n of scan programming bits and having substantially m=log₂(N/n) cells for each of a number n of sets among all N of the scan chains masked by the masking circuit.

2. The electronic scan circuitry of claim 1 including a tester operable to configure the scannable masking qualification circuit in response to detection of unknown state content at a position in the at least one of the plurality of scan chains to disqualify the unknown state content by the masking circuit.

3. The electronic scan circuitry of claim 1 in which the scannable masking qualification circuit is responsive to a modulating input to effectively switch between different masks depending on the state of the modulating input on the scan out cycle.

4. The electronic scan circuitry of claim 1 including a generator circuit coupled to the masking qualification circuit to control the disqualification on a selected scan out cycle and the generator circuit having at least one programmable register responsive to a scan input.

5. The electronic scan circuitry of claim 1 in which the masking qualification circuit includes a multiplexer having a selector input fed from an X-tol enable circuit selected from the group consisting of 1) top level X-tol enable pin, 2) core data register, 3) on-chip X-tol generator.

6. The electronic scan circuitry of claim 1 including a programmable X-tol generator and in which the masking qualification circuit includes a multiplexer having a selector input fed from the X-tol generator.

7. The electronic scan circuitry of claim 1 including at least one cycle identification register, a shift-cycle counter, and a comparator fed by the register and the counter, the comparator coupled to enable the masking circuit to provide masking controls to the masking qualification circuit or not cycle-by-cycle on scan-out of the scan chains.

8. The electronic scan circuitry of claim 1 including a scan-control circuit coupled to the plurality of scan chains to scan them in and out, and the scannable masking qualification circuit is also fed by the decompressor along with the scan chains on scan-in, and the scannable masking qualification circuit is at least partially isolated from control by the scan-out circuit on scan-out.

9. The electronic scan circuitry of claim 1 including a set of scan-in pattern bits elements to enable the masking qualification circuit to provide masking controls to the masking circuit or not, on a cycle-by-cycle basis.

10. The electronic scan circuitry of claim 1 including a functional integrated circuit, the scan chains coupled with parts of the functional integrated circuit, the functional integrated circuit selected from the group consisting of 1) wireless modem circuit, 2) applications processor circuit, 3) digital signal processor circuit, 4) cellular telephone circuit, 5) digital camera circuit, 6) analog circuit, 7) CISC processor, 8) RISC processor, 9) personal computer main microprocessor, 10 application specific integrated circuit (ASIC), 11) gate array.

11. The electronic scan circuitry of claim 1 including a functional integrated circuit chip integrally coupled with the scan chains, chip-level test pins, an on-chip compactor fed by the masking circuit, and an interface including an on-chip test wrapper that couples the chip-level test pins with the decompressor on-chip and the compactor.