Decompressed scan chain masking circuit shift register with log2(n/n) cells
First Claim
1. Electronic scan circuitry comprising:
- a decompressor;
a plurality of scan chains fed by the decompressor;
a masking circuit fed by the plurality of scan chains, the scan chains scannable to scan them out in scan out cycles through the masking circuit; and
a scannable masking qualification circuit coupled to the masking circuit and operable both to select at least one of the plurality of scan chains for disqualification and to execute the disqualification on a selected scan out cycle,the scannable masking qualification circuit including a scan-programmable shift register fed by the decompressor and accommodating at least a number n of scan programming bits and having substantially m=log2(N/n) cells for each of a number n of sets among all N of the scan chains masked by the masking circuit.
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Accused Products
Abstract
Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.
38 Citations
11 Claims
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1. Electronic scan circuitry comprising:
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a decompressor; a plurality of scan chains fed by the decompressor; a masking circuit fed by the plurality of scan chains, the scan chains scannable to scan them out in scan out cycles through the masking circuit; and a scannable masking qualification circuit coupled to the masking circuit and operable both to select at least one of the plurality of scan chains for disqualification and to execute the disqualification on a selected scan out cycle, the scannable masking qualification circuit including a scan-programmable shift register fed by the decompressor and accommodating at least a number n of scan programming bits and having substantially m=log2(N/n) cells for each of a number n of sets among all N of the scan chains masked by the masking circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification