Low drop-out voltage regulator

• US 9,229,464 B2
• Filed: 07/31/2013
• Issued: 01/05/2016
• Est. Priority Date: 07/31/2013
• Status: Active Grant

• Current Assignee: EM Microelectronic - Marin SA (The Swatch Group AG)
• Original Assignee: EM Microelectronic - Marin SA (The Swatch Group AG)
• Inventors: Buescher, Kevin, Buryanec, Jiri
• Primary Examiner(s): Dole, Timothy J
• Assistant Examiner(s): Kyaw, Htet Z
• Application Number:
  US13/955,380
• Publication Number:
  US 20150035506A1
• Time in Patent Office: 888 Days
• Field of Search: 323273-281, 323311-316, 327537-543
• US Class Current: 1/1
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 1/595 semiconductor devices connected in series

Abstract

The voltage regulator comprises a regulation loop (2), which comprises at least a pass transistor (18), a source transistor (28), a sensing transistor (22) and a retention transistor (24), and a stability compensation circuit (10), which comprises a first MOS resistor (12) and a second MOS resistor (14) coupled with the first MOS resistor (12). The gate of the second MOS resistor (14) is coupled to the gate of the pass transistor (18).

Claims

1. A voltage regulator comprising:

a regulation loop comprising at least a pass transistor, a source transistor, a sensing transistor and a retention transistor, and

a stability compensation circuit comprising a first MOS resistor and a second MOS resistor, coupled with the first MOS resistor, wherein a gate of the second MOS resistor is coupled to a gate of the pass transistor,

wherein the stability compensation circuit comprises a second node coupled with a drain of the retention transistor and with a drain of the source transistor, and

wherein the first MOS resistor and the second MOS resistor are arranged in parallel with drains of the first and second MOS resistors connected to the second node.

2. The voltage regulator according to claim 1, wherein the stability compensation circuit comprises a first node coupled with a source of the source transistor and with a source of the pass transistor.

3. The voltage regulator according to claim 1, wherein the stability compensation circuit comprises at least one capacitor coupled by a first terminal with a drain of at least one of the first MOS resistor and the second MOS resistor, and wherein a second terminal of the capacitor is connected to the second node coupled with the drain of the retention transistor and with the drain of the source transistor.

4. The voltage regulator according to claim 1, wherein the second node is coupled to the gate of the second MOS resistor and to the gate of the pass transistor.

5. The voltage regulator according to claim 2, wherein the first MOS resistor and the second MOS resistor are arranged in parallel with sources of the first and second MOS resistors connected to the first node.

6. The voltage regulator according to claim 1, wherein the stability compensation circuit comprises a third resistor between the drains of the first and second MOS resistors and the second node.

7. The voltage regulator according to claim 1, wherein the pass transistor, the source transistor and the sensing transistor are PMOS transistors.

8. The voltage regulator according to claim 1, wherein the retention transistor is an NMOS transistor.

9. An electronic device comprising at least one voltage regulator according to claim 1.