×

Current-starved inverter circuit

  • US 9,229,465 B2
  • Filed: 03/26/2014
  • Issued: 01/05/2016
  • Est. Priority Date: 03/26/2014
  • Status: Expired due to Fees
First Claim
Patent Images

1. A current-starved inverter circuit for generating an output voltage signal based on an input voltage signal, the current-starved inverter circuit comprising:

  • a first current-mirror circuit, connected to first and second supply voltages, for generating a first source current;

    a second current-mirror circuit, connected to the first and second supply voltages, for generating a first sink current;

    a first transistor having a source terminal connected to the first current-mirror circuit for receiving the first source current, a gate terminal for receiving the input voltage signal, and a drain terminal for outputting the output voltage signal;

    a second transistor having a source terminal connected to the second current-mirror circuit for receiving the first sink current, a gate terminal for receiving the input voltage signal, and a drain terminal connected to the drain terminal of the first transistor for outputting the output voltage signal;

    a detector circuit, connected to the drain terminals of the first and second transistors, for receiving the output voltage signal and generating a first detection signal when the output voltage signal exceeds a first threshold voltage level and a second detection signal when the output voltage signal is less than a second threshold voltage level; and

    a current-booster circuit, connected to the detector circuit and the first and second transistors, for receiving the first and second detection signals, generating a second source current based on the first detection signal and a second sink current based on the second detection signal, providing the second source current to the source terminal of the first transistor, thereby pulling up a voltage level of the output voltage signal to the voltage level of the first supply voltage, and providing the second sink current to the source terminal of the second transistor, thereby pulling down the voltage level of the output voltage signal to the voltage level of the second supply voltage.

View all claims
  • 16 Assignments
Timeline View
Assignment View
    ×
    ×