Wake-on-frame for frame processing devices

• US 9,229,518 B1
• Filed: 11/01/2010
• Issued: 01/05/2016
• Est. Priority Date: 11/03/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Pannell, Donald, Chou, Hong Yu
• Primary Examiner(s): Hsu, Alpus H
• Assistant Examiner(s): Houshmand, Hooman
• Application Number:
  US12/916,968
• Time in Patent Office: 1,891 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

Systems, methods, and other embodiments associated with wake-on-frame mechanisms are described. According to one embodiment, an apparatus includes a packet source configured to send packets to a frame processing device and a wake-on-frame mechanism that is selectable by the frame processing device between an enabled state and a disabled state. If the wake-on-frame mechanism is in the enabled state, a packet source that has a frame to send to the frame processing device sends a wake signal to the frame processing device prior to sending the packet. The packet source sends the packet to the frame processing device after receiving a ready signal from the frame processing device.

Claims

1. An apparatus, comprising:

a media access control (MAC) layer comprising a central processing unit (CPU) that performs routing related processing on packets prior to sending the packets to one or more destination devices; and

a physical (PHY) layer comprising a switch configured to send packets to the CPU;

wherein the switch comprises an egress port register that includes a wake-on-frame enable bit that is capable of being set or cleared by the CPU; and

wherein the switch is further configured to;

wait for a new packet to be received for the CPU;

when a new packet is received and the wake-on-frame enable bit is set,

(i) set an interrupt bit in the egress port register to cause an interrupt signal to be sent to the CPU, such that receiving the interrupt signal will cause the CPU to wake up; and

(ii) hold the packet in a queue;

when the wake-on-frame enable bit is clear, send the packet to the CPU.

2. The apparatus of claim 1, wherein:

the switch comprises an Ethernet switch; and

the CPU and Ethernet switch are component parts of a same Ethernet routing device.

3. The apparatus of claim 1, wherein the switch comprises a queue controller configured to accumulate packets after the interrupt bit is set until the wake-on-frame enable bit is cleared.

4. The apparatus of claim 3, wherein the queue controller is configured to order the accumulated packets in the queue according to prioritization rules and identify a highest priority packet for sending first to the CPU.

5. A method, comprising:

operating in a first state in which a switch that is part of a physical (PHY) layer of a device waits for a new packet from an originating device that is

sent to a CPU that is part of a media access (MAC) layer of the device, where the CPU performs routing related processing on packets prior to sending the packets to destination devices, and further where the switch comprises an egress port register that includes a wake-on-frame enable bit that indicates whether the CPU is in an active state or an inactive state;

when a packet is received and the wake-on-frame enable bit indicates that the CPU is in the inactive state, transitioning to a second state in which the switch;

sets an interrupt bit in the egress port register to cause an interrupt signal to be sent to the CPU, such that receiving the interrupt signal will cause the CPU to wake up; and

holds the packet in a queue;

when the wake-on-frame enable bit indicates that the CPU is in the active state, transition ing to a third state in which the switch sends the packet to the CPU.

6. The method of claim 5, further comprising:

while in the second state, accumulating packets in the queue after sending the interrupt signal to the CPU;

while in the third state selecting a highest priority packet from accumulated packets and sending the highest priority packet to the CPU.

7. The method of claim 5, comprising while in the second state detecting a status change of the wake-on-frame enable bit.

8. The method of claim 5, wherein when the wake-on-frame enable bit is set, the CPU is powered off.

9. A router device comprising:

a media access control (MAC) layer comprising a CPU configured to perform routing related processing on packets intended for respective network devices in an Ethernet network; and

a physical (PHY) layer comprising;

an Ethernet switch configured to receive a packet for processing by the CPU, wherein the Ethernet switch includes a plurality of egress ports configured to send packets to the CPU;

wherein the egress ports comprise associated registers that include i) a wake-on-frame enable bit that is capable of being set and cleared by the CPU and ii) a wake-on-frame interrupt bit that, when set by the Ethernet switch, causes an interrupt signal to be sent to the CPU, such that receiving the interrupt signal will cause the CPU to wake up,

wherein the CPU is configured to (i) set the wake-on-frame enable bit prior to entering a low power consumption state, and (ii) clear the wake-on-frame enable bit in response to receiving a wake-on-frame interrupt signal and entering a normal operating state; and

wherein the Ethernet switch is configured to;

wait for a new packet;

when a packet is received and the wake-on-frame enable bit is set, (i) set the wake-on-frame interrupt bit and (ii) hold the packet in a queue;

when the wake-on-frame enable bit is cleared by the CPU, send the packet to the CPU.

10. The device of claim 9, wherein the Ethernet switch includes a queue controller configured to (i) order packets according to prioritization rules and (ii) identify a highest priority packet based on the ordered packets, and, send the highest priority packet to the CPU.