Multi-chip initialization using a parallel firmware boot process
First Claim
1. A method, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system, comprising:
- performing, in parallel, a multi-chip agnostic isolated boot phase operation to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system;
performing, in parallel, a multi-chip aware isolated boot phase operation of each of the processor chips where each of the processor chips has its own separately configured physical address space; and
performing a unified configuration phase operation to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip, wherein performing a multi-chip agnostic isolated boot phase operation comprises;
initializing a chip identifier of each of the processor chips in the plurality of processor chips to have a same master chip identifier; and
setting a virtual to physical address mapping structure of a memory management unit of each of the processor chips such that for each pair of virtual address and physical address, the virtual address is the same as the physical address.
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Abstract
Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.
26 Citations
16 Claims
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1. A method, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system, comprising:
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performing, in parallel, a multi-chip agnostic isolated boot phase operation to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system; performing, in parallel, a multi-chip aware isolated boot phase operation of each of the processor chips where each of the processor chips has its own separately configured physical address space; and performing a unified configuration phase operation to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip, wherein performing a multi-chip agnostic isolated boot phase operation comprises; initializing a chip identifier of each of the processor chips in the plurality of processor chips to have a same master chip identifier; and setting a virtual to physical address mapping structure of a memory management unit of each of the processor chips such that for each pair of virtual address and physical address, the virtual address is the same as the physical address. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system, comprising:
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performing, in parallel, a multi-chip agnostic isolated boot phase operation to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system; performing, in parallel, a multi-chip aware isolated boot phase operation of each of the processor chips where each of the processor chips has its own separately configured physical address space; and performing a unified configuration phase operation to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip, wherein performing a unified configuration phase operation to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip comprises; stopping execution of code on the slave processor chips; reconfiguring a virtual to physical address mapping of the slave processor chips to map virtual addresses to physical addresses of a memory of the master processor chip; and executing, by the slave processor chips, code from the memory of the master processor chip using the reconfigured virtual to address mappings of the slave processor chips.
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9. A computer program product comprising a non-transitory computer readable medium having a computer readable program stored therein, wherein the computer readable program, when executed on a multi-chip data processing system, causes the multi-chip data processing system to:
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perform, in parallel, a multi-chip agnostic isolated boot phase operation to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system; perform, in parallel, a multi-chip aware isolated boot phase operation of each of the processor chips where each of the processor chips has its own separately configured physical address space; and perform a unified configuration phase operation to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip, wherein performing a multi-chip agnostic isolated boot phase operation comprises; initializing a chip identifier of each of the processor chips in the plurality of processor chips to have a same master chip identifier; and setting a virtual to physical address mapping structure of a memory management unit of each of the processor chips such that for each pair of virtual address and physical address, the virtual address is the same as the physical address. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A computer program product comprising a non-transitory computer readable medium having a computer readable program stored therein, wherein the computer readable program, when executed on a multi-chip data processing system, causes the multi-chip data processing system to:
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perform, in parallel, a multi-chip agnostic isolated boot phase operation to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system; perform, in parallel, a multi-chip aware isolated boot phase operation of each of the processor chips where each of the processor chips has its own separately configured physical address space; and perform a unified configuration phase operation to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip, wherein performing a unified configuration phase operation to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip comprises; stopping execution of code on the slave processor chips; reconfiguring a virtual to physical address mapping of the slave processor chips to map virtual addresses to physical addresses of a memory of the master processor chip; and executing, by the slave processor chips, code from the memory of the master processor chip using the reconfigured virtual to address mappings of the slave processor chips.
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Specification