Memory system and wear-leveling method thereof based on erasures and error correction data

• US 9,229,805 B2
• Filed: 09/04/2008
• Issued: 01/05/2016
• Est. Priority Date: 09/13/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yim, Yong-Tae, Jo, Sung-Kue
• Primary Examiner(s): SCHELL, JOSEPH O
• Application Number:
  US12/230,769
• Publication Number:
  US 20090077429A1
• Time in Patent Office: 2,679 Days
• Field of Search: 714/5, 714/7, 714/8, 714/47, 714/723, 714/47.2, 714/6.1, 714/6.13, 714/6.2, 714/47.1, 714/47.3, 714/710
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.

Claims

1. A memory system comprising:

a flash memory device including a plurality of memory blocks, each of the plurality of memory blocks including at least one memory cell; and

a memory controller configured to control the flash memory device such that use of the plurality of memory blocks is distributed based on erasures of the plurality of memory blocks and errors in data stored in the plurality of memory blocks, the memory controller being further configured to distribute the use of the plurality of memory blocks by allocating the plurality of memory blocks into a plurality of groups based on the erasures of the plurality of memory blocks and the errors in data associated with each of the plurality of memory blocks;

wherein

the plurality of groups include a high priority group, an intermediate priority group, and a low priority group.

2. The memory system of claim 1, wherein the memory controller is further configured to distribute the use of the plurality of memory blocks such that use of the plurality of memory blocks is evenly distributed.

3. The memory system of claim 1, wherein the memory controller is further configured to distribute the use of the plurality of memory blocks such that a difference in an amount of use between the plurality of memory blocks is reduced.

4. The memory system of claim 1, wherein the memory controller is further configured to track the erasures of the plurality of memory blocks and correction of errors in the data stored in the plurality of memory blocks, and to distribute the use of the plurality of memory blocks based on the tracked erasures and correction of errors.

5. The memory system of claim 4, wherein the memory controller is further configured to allocate the plurality of memory blocks into the plurality of groups based on the tracked erasures and correction of errors, the memory controller being further configured to distribute the use of the plurality of memory blocks according to the group to which each of the plurality of memory blocks is allocated.

6. The memory system of claim 4, wherein the correction of errors includes the bit values of at least one of the plurality of memory blocks.

7. The memory system of claim 4, wherein the correction of errors includes the bit values of at least one row among rows of memory blocks.

8. The memory system of claim 1, wherein the memory controller allocates the plurality of memory blocks into the plurality of groups depending on a level of priority associated with each of the plurality of memory blocks, the level of priority associated with each of the plurality of memory blocks being assigned based on the erasures of the plurality of memory blocks and the errors in data associated with each of the plurality of memory blocks.

9. The memory system of claim 1, wherein the memory controller is further configured to initially allocate each of the plurality of memory blocks into the high priority group, and then into at least one of the intermediate priority group and the low priority group based on the erasures and the errors in data stored in each of the plurality of memory blocks.

10. The memory system of claim 9, wherein the memory controller is further configured to allocate a first memory block from the high priority group into the intermediate priority group when at least one of a number of 2-bit errors in the first memory block exceeds a first critical value and the number of erasures of the first memory block exceeds a threshold.

11. The memory system of claim 9, wherein the memory controller is further configured to allocate a first memory block from one of the high priority group and the intermediate priority group into the low priority group when a number of 3-bit errors in the first memory block exceeds a second critical value.

12. The memory system of claim 1, wherein the flash memory device and the memory controller constitute a memory card.

13. The memory system of claim 1, wherein the memory controller includes,

a processing unit,

a buffer memory configured to temporarily store data to be stored in or data read from a selected one of the plurality of memory blocks, and

an error correction unit configured to detect errors in data stored in the selected one of the plurality of memory blocks, and to transmit error data to the processing unit.

14. A computing system comprising:

the memory system of claim 1; and

a microprocessor configured to interact with the memory controller to store data in the flash memory.

21. The memory system of claim 1, wherein each of the plurality of groups includes at least one memory block allocated based on the erasures and the errors in data, for use in the memory system.

15. A wear-leveling method, the method comprising:

storing erasures and correction of errors of memory blocks according to use cycles;

distributing use of the memory blocks based on the stored erasures and correction of errors; and

allocating the memory blocks into a plurality of groups based on the stored erasures and the correction of errors;

wherein

the distributing step distributes the use of the memory blocks according to the allocation of the memory blocks, and

the plurality of groups include a high priority group, an intermediate priority group and a low priority group.

16. The method of claim 15, wherein each of the memory blocks is initially allocated to the high priority group, and then to one of the intermediate priority group and the low priority group based on the erasures and the correction of errors associated with the memory block.

17. The method of claim 16, wherein each of the memory blocks is allocated from the high priority group to the intermediate priority group when at least one of a number of 2-bit errors exceed a first critical value and the number of erasures exceed a threshold.

18. The method of claim 16, wherein each of the memory blocks is allocated from one of the high priority group and the intermediate priority group to the low priority group when a number of 3-bit errors exceeds a second critical value.

19. The method of claim 15, wherein the correction of errors includes bit values of at least one of the memory blocks.

20. The method of claim 15, wherein the correction of errors includes bit values of at least one row among rows of the memory blocks.

22. The method of claim 15, wherein each of the plurality of groups includes at least one memory block allocated based on the erasures and the errors in data, for use in the memory system.