Block closure techniques for a data storage device

• US 9,229,806 B2
• Filed: 11/14/2013
• Issued: 01/05/2016
• Est. Priority Date: 11/14/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Mekhanik, Evgeny, Aharonov, Arseniy
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US14/080,626
• Publication Number:
  US 20150135039A1
• Time in Patent Office: 782 Days
• Field of Search: 714/773, 714/763, 714/718
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A data storage device includes a non-volatile memory and a controller. A method includes initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of the non-volatile memory. The method further includes compensating, in response to an event that interrupts programming at the first word line, for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory or by writing dummy data to the second word line.

Claims

1. A method comprising:

in a data storage device including a non-volatile memory and a controller, performing by the controller;

initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of the non-volatile memory; and

in response to an event that interrupts programming at the first word line, compensating for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory or by writing dummy data to the second word line.

2. The method of claim 1, further comprising closing the MLC block to further write operations after compensating for incompletion of the write disturb effect.

3. The method of claim 1, further comprising maintaining at least one common parameter that is common to each word line of the MLC block that stores valid data after compensating for incompletion of the write disturb effect.

4. The method of claim 3, wherein the at least one common parameter indicates threshold voltages used to read data from each word line of the MLC block that stores valid data.

5. The method of claim 3, wherein the at least one common parameter indicates error correcting code (ECC) control data used by an ECC engine of the controller to decode data from each word line of the MLC block storing valid data.

6. The method of claim 3, wherein the at least one common parameter is a time tag.

7. The method of claim 1, wherein the first data corresponds to a lower page, wherein the event occurs while writing the lower page to the first word line, and wherein the second word line is adjacent to the first word line.

8. The method of claim 1, wherein the first data corresponds to an upper page, wherein the event occurs while writing the upper page to the first word line, and wherein a third word line of the MLC block is between the first word line and the second word line.

9. The method of claim 1, wherein the second block is a single-level cell (SLC) block.

10. The method of claim 1, wherein the event includes one or more of a power-down event, a power droop event, a program failure event, a sanitization event, or receiving a host command to close one or more open blocks of the non-volatile memory.

11. A data storage device comprising:

a non-volatile memory that includes a multi-level cell (MLC) block and a second block, wherein the MLC block includes a first word line and a second word line; and

a controller coupled to the non-volatile memory, wherein the controller is configured to initiate a write operation to write first data to the first word line and to compensate, in response to an event that interrupts programming at the first word line, for incompletion of a write disturb effect at the MLC block due to the event by copying second data from the second word line to the second block or by writing dummy data to the second word line.

12. The data storage device of claim 11, wherein the controller is further configured to close the MLC block to further write operations after compensating for incompletion of the write disturb effect.

13. The data storage device of claim 11, wherein the second word line is adjacent to the first word line.

14. The data storage device of claim 11, wherein the MLC block further includes a third word line, and wherein the third word line is between the first word line and the second word line.

15. The data storage device of claim 14, wherein the third word line is adjacent to the first word line.

16. The data storage device of claim 11, wherein the second word line is configured to be disturbed by data writes to the first word line via the write disturb effect.

17. The data storage device of claim 11, wherein the controller is further configured to maintain at least one common parameter that is common to each word line of the MLC block that stores valid data and to operate according to a block closure technique after compensating for incompletion of the write disturb effect.

18. The data storage device of claim 11, wherein the controller is further configured to close the MLC block to further write operations after compensating for incompletion of the write disturb effect and to maintain at least one common parameter that is common to each word line of the MLC block that stores valid data after closing the MLC block.

19. The data storage device of claim 11, wherein the second block is a recovery block reserved for data recovery.

20. The data storage device of claim 11, wherein the second block is a single-level cell (SLC) block.