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Implementing rate controls to limit timeout-based faults

  • US 9,229,839 B2
  • Filed: 01/09/2013
  • Issued: 01/05/2016
  • Est. Priority Date: 01/09/2013
  • Status: Active Grant
First Claim
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1. A computer system comprising the following:

  • one or more processors;

    system memory;

    one or more computer-readable storage media having stored thereon computer-executable instructions that are executable by the one or more processors to cause the computing system to implement rate controls to limit faults detected by timeout and to instantiate the following;

    a monitor module that identifies one or more hardware or software components that have a potential to experience a timeout-based failure within a time frame, wherein the timeout-based failure is a failure in which the one or more hardware or software components is unresponsive for a specified time or takes longer to perform a task than the specified time, wherein the specified time is specified by a timeout value;

    a component failure module that establishes a number of timeout-based failures the one or more hardware or software components are allowed to suffer during the time frame;

    a determining module that determines that the number of timeout-based failures suffered by the one or more hardware or software components within the time frame has exceeded the established number; and

    a timeout value adjusting module that increases the timeout value by a specified amount of time to ensure that fewer than or equal to the established number of timeout-based failures occur within the time frame.

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