Multi-array operation support and related devices, systems and software

• US 9,229,854 B1
• Filed: 10/07/2013
• Issued: 01/05/2016
• Est. Priority Date: 01/28/2013
• Status: Active Grant

• Current Assignee: Radian Memory Systems, Inc.
• Original Assignee: Radian Memory Systems, LLC
• Inventors: Kuzmin, Andrey V., Wayda, James G.
• Primary Examiner(s): Bataille, Pierre-Michel
• Application Number:
  US14/047,193
• Time in Patent Office: 820 Days
• Field of Search: 711/103, 711/170, 711/114
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 16/1847 specifically adapted to static storage, e.g. adapted to flash memory or SSD
• CPC Class Codes: G06F 2015/766 Flash EPROM
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories

Abstract

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Claims

1. An integrated circuit, comprising:

a memory controller to control the performance of memory transactions directed to multiple arrays of flash memory; and

interface circuitry sufficient to exchange information with a host and with the multiple arrays of flash memory;

wherein the memory controller includes logic to, via the interface circuitry, receive one or more requests from the host relating to a transaction operand in the multiple arrays of flash memory, the one or more requests each specifying an address for each of the multiple arrays of flash memory, and to control satisfaction of the one or more requests by the multiple arrays of flash memory; and

wherein the memory controller is configured to preserve page addressing specified by each of the one or more requests relative to any erase unit (EU) position within flash memory, such that any address translation performed by the memory controller for any one of the multiple arrays of flash memory is limited to translating EU location within the one or more arrays of flash memory.

2. The integrated circuit of claim 1, wherein the one or more requests received from the host are each a write request, and wherein the logic is to:

derive a physical address from each address specified by the host, wherein derivation of each physical address comprises one of (a) copy of the address from a corresponding write request received from the host, or (b) shift of the address from the corresponding write request received from the host in a manner corresponding to an integer number of EUs of flash memory; and

transmit at least one command to the multiple arrays in a manner which specifies each physical address derive from the one or more write requests received from the host.

3. The integrated circuit of claim 1, wherein the one or more requests received from the host are each a read request, and wherein the logic is to:

derive a physical address from each address specified by the host, wherein derivation of each physical address comprises one of (a) copy of the address from a corresponding read request received from the host, or (b) shift of the address from the corresponding read request received from the host in a manner corresponding to an integer number of EUs of flash memory; and

transmit at least one command to the multiple arrays in a manner which specifies each physical address derived from the one or more read requests received from the host.

4. The integrated circuit of claim 3, wherein:

the multiple arrays of flash memory are embodied as multiple planes of a single memory die; and

each read request received by the memory controller from the host is one of a first, multi-plane read request

directed to the single memory die or a second, single plane read request directed to the single memory die.

5. The integrated circuit of claim 3, wherein each read request received from the host comprises NVMe-compliant commands that are fused and that are each directed to a single one of the multiple memory arrays of flash memory, and wherein:

the interface circuitry is further to exchange data with the host responsive to each read request via a common connection; and

the logic of the memory controller is to, responsive to the NVMe-compliant commands that are fused, transmit read commands each to a single die and to a single one of the multiple arrays of flash memory plane, the read commands sent in a manner where the memory controller does not await completion of a first read command sent to a first one of the multiple arrays of flash memory before sending a second read command to a second one of the multiple arrays of flash memory.

6. The integrated circuit of claim 1, wherein the integrated circuit further comprises storage to store information representing a multi-plane capability of multi-plane memory and, further, wherein the logic is adapted to provide the information representing the multi-plane capability to the host responsive to a request from the host.

7. The integrated circuit of claim 1, wherein the multiple arrays of flash memory are embodied as a multi-plane flash memory and wherein the integrated circuit further comprises the multi-plane flash memory.

8. The integrated circuit of claim 1, wherein:

the logic of the memory controller is further to receive an erase command from the at least one host, the erase command sufficient to identify one or more associated EUs in respective ones of the multiple arrays of flash memory; and

the logic of the memory controller is further operable to transmit one or more commands to the flash memory to erase all memory cells in the associated EUs.

9. The integrated circuit of claim 1, wherein the flash memory is embodied as a NAND flash memory device, wherein the memory controller is a NAND flash memory controller and, further, wherein the multiple memory arrays comprise a single logical unit number (LUN).

10. The integrated circuit of claim 1, wherein the interface circuitry is operable to electronically communicate with the at least one host via electrical contacts of said integrated circuit, using differential, serial, packetized communications via a connection common to all of the multiple memory arrays.

11. The integrated circuit of claim 1, wherein the memory controller is characterized by not performing logical-to-physical address translation of any write request from the host and is characterized by not performing logical-to-physical address translation of any read request from the host.

12. An integrated circuit, comprising:

a memory controller to control the performance of memory transactions directed to multiple arrays of flash memory; and

interface circuitry sufficient to exchange information with a host and with the multiple arrays of flash memory;

wherein the memory controller includes logic to, via the interface circuitry, receive one or more requests from the host relating to a transaction operand in the multiple arrays of flash memory, the one or more requests each specifying an address for each of the multiple arrays of flash memory, and to control satisfaction of the one or more requests by the multiple arrays of flash memory;

wherein the memory controller is configured to preserve page addressing specified by each of the one or more requests relative to any erase unit (EU) position within flash memory, such that any address translation performed by the memory controller for any one of the multiple arrays of flash memory is limited to translating EU location within the one or more arrays of flash memory;

wherein each array of the multiple arrays comprises memory cells characterized by a program-erase asymmetry, in which each EU of the multiple arrays comprises multiple smallest-size, independently programmable units (PUs) of the multiple arrays; and

wherein

the integrated circuit further comprises storage to store information for each respective PU of each EU of the multiple arrays that indicates whether data stored in the respective PU is stale,

the memory controller is capable of commanding erase of any EU of the multiple arrays for which information in the storage indicates that all constituent PUs are stale, and

the logic of the memory controller is further to receive a multiplane deallocate command from the at least one host, the deallocate command sufficient to identify associated physical addresses in respective ones of the multiple arrays, the logic to mark the information in the storage for each PU corresponding to the associated physical address locations identified by the deallocate command to indicate a stale status.

13. An integrated circuit comprising:

an interface to communicate with a host;

an interface to communicate with a memory device, the memory device of a technology characterized by a program-erase asymmetry, in which each smallest-size, independently erasable unit (EU) in the memory device comprises multiple smallest-size, independently programmable units (PUs) of the memory device;

a memory controller having logic to receive a multi-plane transaction request from the host, and to control performance of the multi-plane transaction request by the memory device;

wherein the multi-plane transaction request specifies a base address location, requests read data from an address in a first plane of the memory device dependent on the base address, requests read data from an address in a second plane of the multi-plane memory device dependent on the base address, and is embodied in the form of one or more commands; and

wherein the memory controller is configured to preserve PU addressing specified by each of the one or more requests relative to any EU position within the memory device, such that any address translation performed by the memory controller for one of the first plane or the second plane is limited to translating EU location within at least one of the first plane or the second plane in the memory device.

14. The integrated circuit of claim 13, wherein the one or more commands are all received by the memory controller prior to transmitting the read data from the first plane to the host and prior to transmitted the read data form the second plane to the host.

15. The integrated circuit of claim 13, further comprising:

storage to store information identifying a multi-plane capability of the memory device; and

logic to receive a request from the host for the information identifying the multi-plane capability of the memory device, and to responsively provide the information identifying the multi-plane capability of the memory device to the host;

wherein the information identifying the multi-plane capability of the memory device includes information identifying a cross-plane addressing limitation required of the memory device for multi-plane commands.

16. The integrated circuit of claim 13, wherein:

the integrated circuit further comprises storage to store information for each PU that indicates whether data stored in the respective PU is stale;

the memory controller is capable of commanding erase of any EU in the multi-plane memory for which information in the storage indicates that all constituent PUs are stale; and

the logic of the memory controller is further to receive a multi-plane deallocate command from the host, the multi-plane deallocate command sufficient to identify physical memory locations in respective planes dependent on a specified base address, the logic to mark the information for each PU corresponding to the linked physical memory locations identified by the deallocate command to indicate a stale status.

17. The integrated circuit of claim 13, wherein:

the logic of the memory controller is to receive a multi-plane erase command from the at least one host, the multi-plane erase command sufficient to identify physical memory locations in respective planes of the memory device dependent on a base address specified by the multi-plane erase command; and

the logic of the memory controller is to transmit one or more single plane erase commands to the multi-plane memory responsive to the multi-plane erase command, to thereby erase all memory cells in at least one EU in each of the respective planes dependent on the base address specified by the multi-plane erase command.

18. The integrated circuit of claim 13, wherein:

the multi-plane transaction request is a first, multi-plane read request;

the logic of the memory controller is to receive a second, single plane read request and to responsively transmit the second, single plane read request to the multi-plane memory; and

wherein the second, single plane read request transmitted by the memory controller to the multi-plane memory specifies a read to only a single one of the planes.

19. The integrated circuit of claim 13, wherein:

the interface to communicate with the host is to exchange data with the host responsive to each read request via a common connection; and

the one or more commands are embodied as a series of fused commands, such that data associated with each command in the series of fused commands is exchanged between the host and the memory controller without regard to whether any prior commands in the series of fused commands have been completed.

20. A method of managing data access directed to multiple arrays of flash memory, the method comprising:

receiving one or more write requests from a host, the one or more write requests specifying write of respective data into one or more addresses in respective arrays of the flash memory;

transmitting at least one write request to the multiple arrays of the flash memory, the at least one write request specifying a physical address responsive to each address received from the host;

receiving one or more read requests from the host that command read of the respective data from the respective arrays flash memory; and

transmitting at least one read request to the multiple arrays of the flash memory, the at least one read request specifying a physical address responsive to each address received from the host;

wherein said method further comprises preserving page addressing specified by each of the one or more write requests and each of the one or more read requests relative to any erase unit (EU) position within flash memory, such that any address translation for any one of the multiple arrays of flash memory responsive to a received host request is limited to translating EU location within the one or more arrays of flash memory.