Refresh scheme for memory cells with next bit table

• US 9,230,634 B2
• Filed: 05/13/2014
• Issued: 01/05/2016
• Est. Priority Date: 12/09/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kim, Jung Pill, Suh, Jungwon, Dong, Xiangyu
• Primary Examiner(s): Gu, Shawn X
• Application Number:
  US14/276,452
• Publication Number:
  US 20150162065A1
• Time in Patent Office: 602 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 2211/4065 Low level details of refresh operations

Abstract

A memory refresh control technique allows flexible internal refresh rates based on an external 1× refresh rate and allows skipping a refresh cycle for strong memory rows based on the external 1× refresh rate. A memory controller performs a memory refresh by reading a refresh address from a refresh address counter, reading a weak address from a weak address table and generating a next weak address value based at least in part on a next bit sequence combined with the weak address. The memory controller compares the refresh address to the weak address and to the next weak address value. Based on the comparison, the memory controller selects between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address.

Claims

1. A memory refresh method within a memory controller, comprising:

reading a refresh address from a refresh address counter;

reading a weak address from a weak address table;

generating a next weak address value based at least in part on a next bit sequence combined with the weak address;

comparing the refresh address to the weak address and to the next weak address value; and

selecting between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address based at least in part on the comparing.

2. The method of claim 1, further comprising:

reading at least one retention bit corresponding to the refresh address;

determining a refresh rate based on the at least one retention bit.

3. The method of claim 2, further comprising determining the next bit sequence based on the at least one retention bit.

4. The method of claim 3, further comprising changing a next bit according to the next bit sequence after each refreshing of the weak address.

5. The method of claim 1, further comprising:

skipping the refresh cycle when the refresh address equals the weak address and does not equal the next weak address;

refreshing the refresh address when the refresh address does not equal the weak address and does not equal the next weak address;

refreshing the weak address when the refresh address equals the weak address and equals the next weak address; and

refreshing both the refresh address and the weak address when the refresh address does not equal the weak address and equals the next weak address.

6. The method of claim 1, further comprising:

reading a strong address from the weak address table; and

skipping refresh cycles of the strong address.

7. The memory refresh method of claim 1, in which the memory controller is integrated in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit and/or a fixed location data unit.

8. A memory refresh apparatus, comprising:

a refresh counter operable to store a refresh address;

a weak address table operable to store a weak address;

a next bit table operable to generate a next weak address based at least in part on next bit values in the next bit table combined with the weak address; and

a refresh controller operable to select between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address based at least in part on comparing the refresh address to the weak address and to the next weak address.

9. The memory refresh apparatus of claim 8, in which the refresh controller is further operable to:

read at least one retention bit corresponding to the refresh address; and

determine a refresh rate based on the at least one retention bit.

10. The memory refresh apparatus of claim 9, the refresh controller is further operable to determine a next bit sequence based on the at least one retention bit.

11. The memory refresh apparatus of claim 10, the refresh controller is further operable to change a next bit according to the next bit sequence after each refreshing of the weak address.

12. The memory refresh apparatus of claim 8, in which the refresh controller is further operable to:

skip the refresh cycle when the refresh address equals the weak address and does not equal the next weak address;

refresh the refresh address when the refresh address does not equal the weak address and does not equal the next weak address;

refresh the weak address when the refresh address equals the weak address and equals the next weak address; and

refresh both the refresh address and the weak address when the refresh address does not equal the weak address and equals the next weak address.

13. The memory refresh apparatus of claim 8, in which the refresh controller is further operable to:

read a strong address from the weak address table; and

skip refresh cycles of the strong address.

14. The memory refresh apparatus of claim 8 integrated in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit and/or a fixed location data unit.

15. A memory controller apparatus, comprising:

a refresh counter to store a refresh address;

a weak address table to store a weak address;

a next bit table to generate a next weak address based at least in part on next bit values in the next bit table combined with the weak address; and

means for selecting between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address based at least in part on comparing the refresh address to the weak address and to the next weak address.

16. The memory controller apparatus of claim 15, further comprising:

means for reading at least one retention bit corresponding to the refresh address;

means for determining a refresh rate based on the at least one retention bit;

means for determining a next bit sequence based on the at least one retention bit; and

means for changing a next bit according to the next bit sequence after each refreshing of the weak address.

17. The memory controller apparatus of claim 15, further comprising:

means for skipping the refresh cycle when the refresh address equals the weak address and does not equal the next weak address;

means for refreshing the refresh address when the refresh address does not equal the weak address and does not equal the next weak address;

means for refreshing the weak address when the refresh address equals the weak address and equals the next weak address; and

means for refreshing both the refresh address and the weak address when the refresh address does not equal the weak address and equals the next weak address.

18. The memory controller apparatus of claim 15 integrated in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit and/or a fixed location data unit.

19. A computer program product for a memory refresh comprising:

a non-transitory computer-readable medium having program code recorded thereon, the program code comprising;

program code to store a refresh address in a refresh counter;

program code to store a weak address in a weak address table;

program code to generate a next weak address based at least in part on next bit values in a next bit table combined with the weak address; and

program code to select between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address based at least in part on comparing the refresh address to the weak address and to the next weak address.

20. The computer program product of claim 19, in which the recorded program code further comprises:

program code to read at least one retention bit corresponding to the refresh address;

program code to determine a refresh rate based on the at least one retention bit;

program code to determine a next bit sequence based on the at least one retention bit; and

program code to change the next bit according to a next bit sequence after each refreshing of the weak address.